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  cx28560 hdlc controller data sheet 28560-DSH-001-B april 2004
? 2004, mindspeed technologies tm , inc. all rights reserved. information in this document is provided in connection with mindspeed technologies tm ("mindspeed tm ") products. these materials are provided by mindspeed as a service to its customers and may be used for informational pur- poses only. except as provided in mindspeed?s terms and conditions of sale for such products or in any separate agreement related to this document, mindspeed assumes no liability wh atsoever. mindspeed assumes no respon- sibility for errors or omissions in these materials. mi ndspeed may make changes to specifications and product descriptions at any time, without notice. mindspeed makes no commitment to update the information and shall have no responsibility whatsoever for conf licts or incompatibilities arising from future changes to its specifications and product descriptions. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. these materials are provided "as is" withou t warranty of any kind, either express or implied, relating to sale and/or use of mi ndspeed products including liability or war- ranties relating to fitness for a particular purpose, consequential or incidental dam- ages, merchantability, or infringement of any patent, copyright or other intellectual property right. mindspeed further does not warrant the accuracy or completeness of the information, text, graphics or othe r items contained within these materials. mindspeed shall not be liable for any special, indirect, incidental, or consequential damages, including without limitation, lost revenues or lost profits, which may result from the use of these materials. mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. mindspeed customers using or selling mindspeed pr oducts for use in such applications do so at their own risk and agree to fully indemnify mindspeed for any damages resulting from such improper use or sale. 28560-DSH-001-B mindspeed technologies? advance information ordering information model number package operating temperature ? tbga 40 mm x 40 mm ?40 c to +85 c revision history revision level date description a advance december 2000 initial release (document no. 101302a). a advance april 2001 500031a formerly document no. 101302a. correction of technical inaccuracies for first full release. b advance october 2001 corrected fuzzy drawings ( chapter 8.0 ). in table 9-3 , replaced signal names to match pin description. created table 1-13 for onesec signal. c advance july 2002 based on preliminary characte rization, updated ebus timing specification ( section 8.2.4 ) and few other electr ical specifications ( chapter 8.0 ). corrected technical inaccuracies. a advance march 2003 released with new docum ent number: 28560-dsh-001-a. b advance april 2004 corrected pin assignment on ad [6] - ad[10] in table 9-3. tdata[0] mislabell ed tdat[0] in table 9-3. rdat[20] mislabel l ed rdat[16] in table 9-3.
28560-DSH-001-B mindspeed technologies? iii advance information cx28560 hdlc controller the cx28560 is an advanced multichannel synchronous communications controller (musycc? ) that formats and deformats up to 2047 hdlc channels in a cmos integrated circuit. musycc operates at l ayer 2 of the open systems interconnection (osi) protocol reference model and provides a comprehensive, high-density solution for processing hdlc channels for inter-networking applications. all packet data passed between the system and the cx28560 is passed across the pos-phy interface (pos-phy). the pos-ph y operates in packet mode as a 32-bit wide point-to-point interface at 100 mhz. data is transferred in fragments of user- configurable length (minimum 32 bytes per fragment). the cx28560 supports a pci interface for initial configuration as well as to perform dynamic activation and deactivation of channels. in addition, the cx28560?s configuration and performance monitoring counters can be read over the pci interface. the scheduling system for the receive and tran smit data flow is based on the unique flexiframe? algorithm. flexiframe enables efficient memory utilization and provides support for various channels operating at extremely differ ent rates. flexiframe allows dynamic resizing of every channel?s rate wi thout affecting the other channels. the order in which message fragments are transf erred across the pos-phy is fixed by the flexiframe structure, each fragment having been tagged with a 4-byte fragment header. the fragment header contains the channel number and relevant status information. a dedicated 8-bit bus provides the system the necessary feedback to determine the amount of data contained in each channel?s tran smit buffers. this is achieved by the cx28560 sending requests to the system for more transmit data. in the receive direction, the cx28560 operates aut onomously without any need for system intervention or guidance. functional block diagram bi-directional 32 b, 100 mhz pos-phy bus (data) unit-directional 8 b 100 mhz tx flowconductor bus pos-phy i/f interrupt controller pci i/f ebus bridge pci bus 2.2 expansion bus host service unit rx and tx serial line processors rx and tx serial interface units port 0 . . . port 1 port 31 miscellaneous jtag etc. internal buffer controllers flexiframe scheduler advance information this document contains information on a product under development. the parametric information contains target parameters that are subject to change. distinguishing features 2047-channel hdlc controller osi layer 2 protocol support 32-bit full duplex sta ndard pos-phy level 3 bus aggregate bandwidth of 700 mbps full duplex 32 bits, 33 mhz pci 2.2 bus interface for configuration and monitoring dedicated feedback bus for tx buffers fill level 32 independent serial interfaces support: t1 data stream n * 64 kb/s data stream tsbus interfaces unchannelized data stream configurable logical channels standard ds0 (56, 64 kbps) hyperchannel (n x 64) channels? bit rate can be dynamically changed. per channel protocol mode selection per-channel message length check select no length checking select from three 14-bit registers to compare message length hdlc maximum packet length 16,384 bytes 3 separate hdlc mode s, configurable per channel: no fcs 16-bit fcs 32-bit fcs transparent (not hdlc) mode autonomous rx operati on and arbitration between the channels selectable endian configuration for control information (pci) per-channel bu ffer management full set of 10 performance monitoring counters per channel transfer of partial hdlc messages over the pos-phy interface low power, 1.8 volt core, 3.3 volt i/o, cmos operation. local expansion bus in terface (ebus) for accessing non-pci co mponents (framers, lius) jtag boundary sc an access port 40 mm tbga package
28560-DSH-001-B mindspeed technologies? iv advance information cx28560 data sheet the cx28560 supports four serial port modes: conventional ch annelized, conventional unchannelized, conventional t1, and tsbus. in tsbus mode, the cx 28560 supports a special mindspeed proprieta ry interface: the tsbus (time slot bus). the tsbus allows for mapping of all tributary signals to time sl ots for a transmission to external devices, such as mindspeed?s bam (broadband access multiplexer) d evice family. the tsbus interface consists of two serial interfaces: a 51.84 mhz payload interface and a 12.96 mhz overhead interface. payload of tributary signals is mapped to time slots on the payload bus allowing for a transmission of the following signals? payload: ? 28 x ds1, vt1.5, or vc-11 signals ? 21 x e1, vt2.0, or vc-12 signals ? 1 x ds3, e3, or sts-1 signal overhead information including sonet/sdh/pdh overhead and cont rol information is transmitted in time slots on the overhead ts-bus interface. the first 12 ports of the cx28560, when configured in ts bus mode, also support ds0 extraction.
28560-DSH-001-B mindspeed technologies? v advance information contents figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xv 1.0 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 external interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.1 cx28560 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.1.1 cx28560 serial port modes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.1.2 cx28560 serial port throughput limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.1.3 tsbus?time slot bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.2 system-side interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.2.1 pos-phy interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.2.1.1 pos-phy data interface?cx28560 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.2.1.2 transmit flowconductor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.2.2 expansion bus (ebus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.2.3 pci bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.3 feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.4 applications examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.5 system overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.7 data flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.7.1 receive data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.7.2 transmit data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.8 cx28560 pin list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.8.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
contents cx28560 data sheet vi mindspeed technologies? 28560-DSH-001-B advance information l 2.0 host interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1 pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.1.1 pci initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 3 2.1.1.2 pci bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.1.3 fast back-to-back transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.1.4 pci configuration space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2 pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.1 pci master and slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.1.1 register 0, address 00h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.1.2 register 1, address 04h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.1.3 register 2, address 08h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.1.4 register 3, address 0ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.1.5 register 4, address 10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.2.1.6 register 5?10, address 14h?28h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.2.1.7 register 11, address 2ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.2.1.8 register 12?14, address 30h?38h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.2.1.9 register 15, address 3ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.2.2 pci reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.2.3 pci throughput and latency considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.2.4 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3 pos-phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.1 pos-phy interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.1.1 pos-phy registered mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.1.2 pos-phy data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.1.3 pos-phy flow conductor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.3.1.4 receive pos-phy initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.3.1.5 transmit pos-phy initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 3.0 expansion bus (ebus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 ebus?operational mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.1.1 initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.1.2 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.1.3 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.1.4 address duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.1.5 data duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.1.6 bus access interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.1.7 pci to ebus interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.1.8 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.1.9 arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.1.10 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.1.10.1 multiplexing address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
28560-DSH-001-B mindspeed technologies? vii advance information cx28560 data sheet contents 4.0 cx28560 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 serial interface unit (siu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3 serial line processor (slp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.4 buffer controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.6 serial port interface definition in conventional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.6.1 frame synchronization flywheel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8 4.6.2 change of frame alignment (cofa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.6.3 out of frame (oof)/frame recovery (frec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.6.4 general serial port interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.6.5 channel clear to send (cts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-10 4.6.6 frame alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.7 serial port interface definition tsbus mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.7.1 tsbus frame synchronization flywheel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.7.2 tsbus group synchronization flywheel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.7.3 tsbus change of frame a lignment (cofa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.7.4 tsbus out of frame (oof )/frame recovery (frec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.7.5 tsbus frame alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-12 4.7.6 tsbus channel clear to send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -12 4.7.7 tsbus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.7.7.1 payload tsbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.7.7.2 overhead tsbus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 5.0 the cx28560 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 memory architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1 register map and shared memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.2.1 service request mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5 5.2.1.1 service request descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.2.1.2 service request descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.2.2 port alive registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.2.3 soft chip reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.3 interrupt level descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3.1 interrupt queue register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3.1.1 interrupt descr iptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.3.1.2 interrupt status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 5.3.2 interrupt handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.3.2.1 initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -20 5.3.2.2 interrupt descriptor ge neration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.3.2.3 inta# signal line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 5.4 global configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.5 ebus configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.6 pos-phy control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.6.1 transmit pos-phy thresholds register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.6.2 transmit pos-phy control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.6.3 receive pos-phy control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5
contents cx28560 data sheet viii mindspeed technologies? 28560-DSH-001-B advance information l 5.7 receive path registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5.7.1 rslp channel status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5.7.2 rslp channel configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5.7.3 rslp maximum message length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.7.4 rbuffc channel configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.7.5 rbuffc flexiframe memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -30 5.7.6 rbuffc flexiframe control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 0 5.7.7 rbuffc data fifo size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 31 5.7.8 rbuffc fragment size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 31 5.7.9 rbuffc flexiframe slot time register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5.7.10 rbuffc counter memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-32 5.7.11 rsiu time slot configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 3 5.7.11.1 receive time slot map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 5.7.11.2 rsiu time slot configuration descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 5.7.12 rsiu time slot pointer allocation register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 5.7.12.1 time slot allocation rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 5.7.13 rsiu group map pointer allocation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 5.7.14 rsiu group state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 5.7.15 rsiu port configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 5.8 transmit path registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 5.8.1 tslp channel status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 5.8.2 tslp channel configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 5.8.3 tbuffc channel configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 5.8.4 tbuffc flexiframe memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 5.8.5 tbuffc flexiframe control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 3 5.8.6 tbuffc data fifo size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 44 5.8.7 tbuffc flexiframe slot time register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44 5.8.8 tbuffc counter memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-45 5.8.9 tsiu time slot configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5 5.8.9.1 transmit time slot map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45 5.8.9.2 tsiu time slot configuration descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47 5.8.10 tsiu time slot pointer allocation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 5.8.10.1 time slot allocation rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 5.8.11 tsiu group time slot map pointers register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50 5.8.12 tsiu group state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50 5.8.13 tsiu port configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-51 5.9 pos-phy transaction headers and packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 5.9.1 receive pos-phy data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 5.9.2 transmit pos-phy data bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54 5.9.3 transmit flow conductor bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55
28560-DSH-001-B mindspeed technologies? ix advance information cx28560 data sheet contents 6.0 functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1.1 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1.1.1 hard pci reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.1.1.2 soft chip reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.1.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.1.2.1 pci configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.1.2.2 service request mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.1.2.3 global configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.1.2.4 interrupt queue configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.1.2.5 pos-phy configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.1.2.6 chip-level configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.1.2.7 channel and port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.1.2.8 typical initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.2 channel operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.2.1 channel activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.2.1.1 transmit channel activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.2.1.2 receive channel activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.2.2 channel deactivation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.2.2.1 transmit channel deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.2.2.2 receive channel deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.2.3 channel reactivation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.3 port operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.3.1 unmapped time slots. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.3.2 enabling a port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.3.3 disabling a port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 7.0 basic operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1 protocol-independent operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.1 transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.2 receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.2 hdlc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.2.1 frame check sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2.2 opening/closing flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2.3 abort codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2.4 zero-bit insertion/deletion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.5 message configuration bits?h dlc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.5.1 idle code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.5.2 intermessage pad fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.5.3 ending a message with an abort or sending an abort sequence . . . . . . . . . . . . . 7-5 7.2.6 transmit events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.2.6.1 end of message (eom). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.2.6.2 transmit cofa recovery (tcrec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.2.7 receive events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.2.7.1 end of message (eom). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.2.7.2 change to abort code (chabt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
contents cx28560 data sheet x mindspeed technologies? 28560-DSH-001-B advance information l 7.2.7.3 chabt interrupt (if idleien = 1 in chapter 5.0, rslp channel configuration register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.2.7.4 change to idle code (chic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.2.7.5 frame recovery (frec) or generic serial port (sport) interrupt . . . . . . . . . . . 7-6 7.2.7.6 receive cofa recovery (rcrec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.2.8 transmit errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.2.8.1 transmit underrun (buff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.2.8.2 transmit change of frame alignment (cofa). . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.2.8.3 buffer controller channel fifo overflow (bovflw) . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.2.9 receive errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.2.9.1 receive overflow (buff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.2.9.2 receive change of frame alignment (cofa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.2.9.3 out-of-frame (oof) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.2.9.4 frame check sequence (fcs) error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.2.9.5 octet alignment error (align) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 7.2.9.6 abort termination (abt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 7.2.9.7 long message (lng) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 7.2.9.8 short message (sht) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 7.3 transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.3.1 message configuration bits?transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.3.1.1 idle code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7- 13 7.3.1.2 intermessage pad fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.3.1.3 ending a message with an abort or sending an abort sequence . . . . . . . . . . . . 7-13 7.3.2 transmit events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7.3.2.1 end of message (eom). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7.3.3 receive events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7.3.3.1 end of message (eom). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7.3.3.2 frame recovery (frec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7.3.3.3 receive cofa recovery (rcrec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7.3.4 transmit errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7.3.4.1 transmit underrun (buff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7.3.4.2 transmit change of frame alignment (cofa). . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 7.3.4.3 buffer controller channel fifo overflow (bovflw) . . . . . . . . . . . . . . . . . . . . . . 7-16 7.3.5 receive errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 7.3.5.1 receive overflow (buff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 7.3.5.2 receive change of frame alignment (cofa) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 7.3.5.3 out of frame (oof) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 7.3.5.4 short cofa (sht cofa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 8.0 electrical and mechanical specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1 electrical and environmental specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 8.1.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.1.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2 timing and switching specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2.2 host interface (pci) timing and switching characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
28560-DSH-001-B mindspeed technologies? xi advance information cx28560 data sheet contents 8.2.3 data interface (pos-phy) timing and switching characteristics . . . . . . . . . . . . . . . . . . . . . . 8-7 8.2.4 expansion bus (ebus) timing and switching characteristics . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.2.5 ebus arbitration timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 3 8.2.6 serial interface timing and switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8.2.7 test and diagnostic interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8- 20 8.3 package thermal specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.4 mechanical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 9.0 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 a. counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.1 one-second pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.2 counter latching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-2 a.3 counter descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 a.3.1 receive counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 a.3.1.1 multiple errors on a single message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 a.3.2 transmit counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-4 a.4 reading counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-5 a.4.1 receive direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-5 a.4.2 transmit direction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-6 b. flexiframe algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 b.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 b.2 new flexiframe required. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-2 b.3 algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-2 b.3.1 splitting channel bit rates into groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b -2 b.3.2 harmonic bit rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.3.3 calculating step size per group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-4 b.3.4 assigning channels to slots/tracks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-5 b.4 pseudo-code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-5 b.4.1 assigning input channels to groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b -5 b.4.1.1 computing the number of tracks to be used . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-7 b.4.2 building the output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-8 b.5 analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-9 b.5.1 equations for analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-10 b.5.2 solution for equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-10 b.5.3 building the flexiframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-11 c. flow conductor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .c-1 c.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1 c.2 example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-3 d. tsbus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-1 d.1 connection between cx28560 and other tsbus device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-1 d.1.1 vsp mapping of intermixed digital level 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-5 d.2 timing details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-7 d.2.1 payload bus, ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .d-7 d.2.2 transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-8 d.2.3 receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-10
contents cx28560 data sheet xii mindspeed technologies? 28560-DSH-001-B advance information l d.3 overhead bus, ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-15 d.3.1 transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-15 d.3.2 receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-15 e. buffer controller fifo size calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-1 e.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-1 e.1.1 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-1 e.1.2 assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-2 e.1.3 overkill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-3 e.2 expanding data in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-4 e.2.1 ending a 57-byte message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-4 e.2.2 byte message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-5 e.2.3 ending a fragment with no end of message. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-5 e.2.4 not ending a fragment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-5 e.3 general buffer wastage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-6 e.4 overview of analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-6 e.4.1 preliminary calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-6 e.5 receive analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-7 e.5.1 preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-7 e.5.1.1 missed services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-7 e.5.2 calculation of step size between services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-9 e.5.2.1 starting position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-9 e.5.2.2 servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e- 10 e.5.2.3 57-byte messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-10 e.5.2.4 last bit (byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-10 e.5.3 example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-11 e.5.3.1 channels of same bit rate, large minimum packet size . . . . . . . . . . . . . . . . . . e-11 e.6 transmit fifo calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-12 e.6.1 service request scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .e-12 f. example of little-big endian byte ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . f-1 g. example of an arbitration for fast and non-fast back-to-back transactions . . . . . . . .g-1 h. pci utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . h-1 h.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . h-1 h.2 analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . h-1 h.2.1 internal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . h-1 h.2.2 conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . h-2 i. maximum number of channels calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i-1
cx28560 figures hdlc controller 28560-DSH-001-B mindspeed technologies? xiii advance information figures figure 1-1. oc-12 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 figure 1-2. system overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 figure 1-3. cx28560 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 figure 2-1. the cx28560 host interface functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 figure 3-1. ebus functional block diagram with local mpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 figure 3-2. ebus functional block diagram without local mpu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 figure 3-3. ebus connection, non-mult iplexed address/data, 8 framers, no local mpu . . . . . . . . . . 3-9 figure 3-4. ebus connection, non-mult iplexed address/data, 16 framers, no local mpu . . . . . . . . 3-10 figure 3-5. ebus connection, multiplexed address/data, 8 fr amers, no local mpu . . . . . . . . . . . . . 3-11 figure 3-6. ebus connection, multiplexed address/data, 4 fr amers, no local mpu . . . . . . . . . . . . . 3-11 figure 4-1. serial interface functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 figure 5-1. interrupt notification to host. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 figure 5-2. receive time slot map pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-33 figure 5-3. transmit time slot map pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-46 figure 8-1. pci clock (pclk) waveform, 3.3 v clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 figure 8-2. pci output timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 figure 8-3. pci input timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 figure 8-4. transmit physical timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 figure 8-5. receive physical timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 figure 8-6. ebus reset active to inactive delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-11 figure 8-7. ebus output timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 -12 figure 8-8. ebus input timing waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-12 figure 8-9. ebus write/read cycle, intel-styl e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-13 figure 8-10. ebus write/read cycle, motorola-style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8- 14 figure 8-11. serial interface clock (rclk,tclk ) waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 figure 8-12. serial interface data input waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-16 figure 8-13. serial interface data delay output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 figure 8-14. transmit and receive t1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-18 figure 8-15. transmit and receive channelized non-t1 (i.e., n x 64) mode . . . . . . . . . . . . . . . . . . . . . 8-19 figure 8-16. jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 figure 8-17. package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 figure 9-1. pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 figure c-1. data and command stor age in internal buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-2 figure d-1. cx28560 time slot interface pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-2 figure d-2. source/destination of tsbus bl ock line-side signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-4 figure d-3. payload time slot bus transmit data (tsb_tdat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-8 figure d-4. payload time slot bus transmit stuff indicator (tsb_tstuff) . . . . . . . . . . . . . . . . . . . . . d-9 figure d-5. payload time slot bus receive data (tsb_rdat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-10 figure d-6. payload time slot bus receive stuff indicator (t sb_rstuff) . . . . . . . . . . . . . . . . . . . . . d-11
figures cx28560 hdlc controller xiv mindspeed technologies? 28560-DSH-001-B advance information figure d-7. tsbus interface to cx28560 transmit sync ti ming (tsb_tsynco) . . . . . . . . . . . . . . . d-12 figure d-8. tsbus interface to cx28560 transmit sync ti ming (tsb_tsynci) . . . . . . . . . . . . . . . . d-13 figure d-9. tsbus interface to cx28560 receive sync timing (tsb_rsync) . . . . . . . . . . . . . . . . . d-14 figure e-1. buffc internal fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-2 figure e-2. worst case on a frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-7 figure e-3. servicing a normal channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-8 figure e-4. worst case servicing of a mid-range channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-8 figure e-5. worst case servicing of a mid-range channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-10 figure g-1. pci burst write: two 32-bit fast back-to-back transactions to same target . . . . . . . . . . . g-1 figure g-2. pci burst: two 32-bit transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . g-2
cx28560 tables hdlc controller 28560-DSH-001-B mindspeed technologies? xv advance information tables table 1-1. supported cx28560 serial port modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -2 table 1-2. allowed cx28560 port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 table 1-3. data path configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 table 1-4. examples of serial port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4 table 1-5. pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 table 1-6. serial interface (general) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 table 1-7. with ds0 extraction mode additional pins (12 port s only) . . . . . . . . . . . . . . . . . . . . . . . . 1-21 table 1-8. cx28560 pos-phy interface (transmit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 table 1-9. cx28560 pos-phy interface (receive). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 3 table 1-10. pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 table 1-11. ebus interface (communication with peripheral components) . . . . . . . . . . . . . . . . . . . . . 1-27 table 1-12. boundary scan and test access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 table 1-13. performance monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 table 2-1. pci configuration space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 table 2-2. register 0, address 00h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 table 2-3. register 1, address 04h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 table 2-4. register 2, address 08h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 table 2-5. register 3, address 0ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 table 2-6. register 4, address 10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 table 2-7. register 5?10, address 14h?28h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11 table 2-8. register 11, address 2ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 table 2-9. register 12?14, addr ess 30h?38h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 table 2-10. register 15, address 3ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 table 3-1. ebus service request descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 table 3-2. ebus service request field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -4 table 5-1. pci register map (direct access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 table 5-2. indirect register map address accessible via se rvice request mechanism . . . . . . . . . . . . . 5-3 table 5-3. service request length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 table 5-4. service request pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 table 5-5. service request descriptor?opcode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 table 5-6. device configuration descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 table 5-7. dcd field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 table 5-8. ebus configuration service request descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 table 5-9. ecd field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 table 5-10. channel configuration service request descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 table 5-11. ccd field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 table 5-12. receive port alive register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 table 5-13. transmit port alive register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 table 5-14. interrupt queue pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
tables cx28560 hdlc controller xvi mindspeed technologies? 28560-DSH-001-B advance information table 5-15. interrupt queue length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 table 5-16. buffc interrupt descriptors format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14 table 5-17. non-buffc interrupt descriptors format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 7 table 5-18. interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 table 5-19. global configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 table 5-20. ebus configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 table 5-21. transmit pos-phy thresholds register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 4 table 5-22. transmit pos-phy control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 table 5-23. receive pos-phy control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-25 table 5-24. rslp channel status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 table 5-25. rslp channel configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 table 5-26. maximum message length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 28 table 5-27. rbuffc channel configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 29 table 5-28. rbuffc flexiframe memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 table 5-29. rbuffc flexiframe control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-30 table 5-30. rbuffc data fifo size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 table 5-31. rbuffc fragment size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-31 table 5-32. rbuffc flexiframe slot time register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 table 5-33. rbuffc counter memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 table 5-34. rsiu ts/group map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 table 5-35. rsiu group map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 table 5-36. rsiu time slot/group map pointer allocation register . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 table 5-37. rsiu group map pointer allocation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 table 5-38. rsiu group state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 table 5-39. rsiu port configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 table 5-40. tslp channel status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 table 5-41. tslp channel configuration regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 table 5-42. tbuffc channel configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 41 table 5-43. tbuffc flexiframe memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 table 5-44. tbuffc flexiframe control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-43 table 5-45. tbuffc data fifo size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44 table 5-46. tbuffc flexiframe slot time register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44 table 5-47. tbuffc counter memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45 table 5-48. tsiu ts/group map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47 table 5-49. tsiu group map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48 table 5-50. tsiu time slot/group map pointer allocation regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 table 5-51. tsiu group map pointers register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-50 table 5-52. tsiu group state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50 table 5-53. tsiu port configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51 table 5-54. cx28560 receive header format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-53 table 5-55. cx28560 transmit data header format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 4 table 5-56. cx28560 flow conductor packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 table 8-1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 table 8-2. recommended 3.3 v operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 table 8-3. dc characteristics for 3.3 v oper ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 table 8-4. pci interface dc specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
cx28560 tables hdlc controller 28560-DSH-001-B mindspeed technologies? xvii advance information table 8-5. pci clock (pclk) waveform parameters, 3.3 v clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 table 8-6. pci reset parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 table 8-7. pci input/output timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5 table 8-8. pci i/o measure conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 table 8-9. transmit interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 table 8-10. receive interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 table 8-11. ebus reset parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 table 8-12. ebus input/output timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8- 11 table 8-13. ebus input/output measure condit ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 2 table 8-14. serial interface clock (rclk, tclk) parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 table 8-15. serial interface input/output timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 table 8-16. serial interface input/output measu re conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 table 8-17. test and diagnostic interface timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 table 8-18. test and diagnostic interface switching characteris tics . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 table 9-1. pin list for 28560 hdlc controller?alphabetic orde r (1 of 2) . . . . . . . . . . . . . . . . . . . . . . 9-2 table 9-2. bga assignments for power (vddc, vddo and vgg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 table 9-3. signals (1 of 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 table a-1. service request routine field for counter read (receive) . . . . . . . . . . . . . . . . . . . . . . . . . . a-5 table a-2. receive counters in shar ed memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-6 table a-3. service request routine field for counter read (transmit) . . . . . . . . . . . . . . . . . . . . . . . . . a-6 table a-4. transmit counters in shared memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-7 table b-1. the flexiframe structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-4 table b-2. flexiframe analysis parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-9 table d-1. system side interface: payload time slot bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-3 table d-2. system side interface: overhead time slot bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-3 table d-3. system side interface: overhead time slot bus fr ame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-5 table d-4. vsp mapping of intermixed digital level 2 signals containing either ds1 or e1 signals . . . d-6 table e-1. data/status combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-3 table e-2. servicing sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-11 table f-1. little endian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . f-1 table f-2. big endian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . f-1
tables cx28560 hdlc controller xviii mindspeed technologies? 28560-DSH-001-B advance information
28560-DSH-001-B mindspeed technologies? 1 - 1 advance information 1.0 introduction the cx28560 is a 2047-channel communications controller targeted at synchronous link layer applications that provides a comprehensive, high density solution for hdlc internetworking applications. ?hdlc/sdlc lapb, lapd  digital access cross-connect (dac)  frame relay switches and access devices (frad)  isdn-d channel signaling x.25 smds/atm dxi  lan/wan access data  sonet/sdh add/drop multiplexers (adms)  terminal multiplexers (tms)  high range/gigabit routers the cx28560 hdlc controller in terfaces to 32 independent serial data streams such as ds0, t1/e1, t3/e3, sts-1/stm-1. data is transferred between the system and the cx28560 across a standard, high performance, 32-bit pos-phy bus as fragments of complete packets. in the transmit directio n, the cx28560 provides the system with buffer state information across an 8-bit/100 mhz standard pos-phy bus level 3 (flowconductor? bus).
1-2 mindspeed technologies? 28560-DSH-001-B advance information introduction cx28560 data sheet 1.1 external interfaces 1.1.1 cx28560 serial interface each serial port can be configured to suppor t different types of interfaces. each of the cx28560?s 32 full-duplex serial ports are individually programmable to operate as conventional or tsbus serial ports. the cx28560 supports five different operating modes for each of its serial ports (some limitations apply, see below): co nventional unchanne lized, conventional channelized, conventional t1, tsbus (no ds0 extraction), and tsbus (with ds0 extraction). a brief description of e ach of these modes is listed in table 1-1 , or, for a fuller description, see chapter 4.0 . 1.1.1.1 cx28560 serial port modes description in all conventional modes the group sync signals are ignored. table 1-1. supported cx28560 serial port modes (1 of 2) cx28560 serial port mode description conventional unchannelized (1) the serial input/output data stre am is a bit stream without any framing or alignment. the bit stream belongs to a single l ogical channel. the cx28560 conv entional unchannelized mode can be configured for all 32 serial ports. the first twelve seri al ports can operate unchannelized t3/e3, hssi, or sts-1/stm-1 bit stream up to 52 mbps per serial interface (for reference, see section 1.1.1.2 ). conventional channelized (1)(2) the serial bit stream is treated as a frame of n time slots (where n is 8192, given that other restrictions are met). the maximum ba ndwidth embedded into the pcm highway for the first thirteen ports is sts-1 rate (51. 84 mbps). the byte a nd frame synchronization performed is based on receive and transmit sy nc pulse (rsync and t sync). (for a detailed description of th ese signals, see chapter 4.0 .) conventional t1 mode (1) the serial bit stream is treated as a frame of 24 time slots and the firs t bit of each t1 frame is discarded by the cx28560 henc e, if the serial port is co nfigured in t1 mode, the port operates according to th e t1 framing definition. tsbus (2)(3) (no ds0 extraction) the tsbus serial interface bit stream is treated as a frame of n time slots or variable bandwidth time slots called virtual serial ports (vsps) where n is defined as 5, and the aggregate number of time slot s across all ports in any di rection does not exceed the 8192 available time slots in each direction, (receiv e or transmit). byte synchronization and frame synchronization is perf ormed based on the ts bus sync pulse tstb (i.e., bus strobe). mixed t1/e1 paths in one t3, mixed vt1.5/vt2 paths mapped to vtgs in one sts1, and mixed vc11/vc12 paths ma pped to tug2 in stm-1 are a llowed using this serial port configuration. no ds0 extrac tion is performed, but separa te logical cha nnels can be configured within the frame. tsbus (2)(4) (with ds0 extraction) this mode is identical to tsbus no ds0 extrac tion, except that furt her multiplexing can be performed by synchronizing t1/e1 frames within the sts-1 bit stream with the group sync pulse (rgsync and tgsync). according to th is pulse, ds0 extraction is performed. normally this mode will be used to extract ds0 signals fr om t1/e1 frames within a higher multiplexed hierarchy (see appendix d for full explanation). hy per channeling of channels within groups is possible. a minimum of 5 slots must be programmed per group.
28560-DSH-001-B mindspeed technologies? 1 - 3 advance information cx28560 data sheet introduction 1.1.1.2 cx28560 serial port throughput limits each of the cx28560 serial ports can be conf igured to operate in any of the preceding operational modes. the following restrictions apply:  the overall number of time slots cannot exceed 8192.  the overall number of channels cannot exceed 2047.  the total accumulated speed of all seri al port clocks in either receive or transmit direction must be less than 800 mhz.  the aggregated serial port data bandwidth cannot exceed 700 mbps in each direction.  the maximum speed per port is less than 52 mbps (hssi) where the maximum number of high speed ports is 12.  the maximum number of ports that can run 44.7 mbps (t3) is 15.  the maximum number of ports that can run 32.768 mbps (e3) 21. allowed cx28560 port configurations are listed in table 1-2 . note(s): 1. a conventional serial port is de fined as 7 input/output signals as follows: transmit cloc k (tclk), transmit synchronization (tsync), transmit data (tdat), receive clock (rclk), receive synchr onization (rsync), receive data (rdat), receive out- of-frame, or clear to send (roof/ cts). in conventional mode, the tgsync and rgsync signal s are ignored. (for a detailed description of th ese signals, see section 4.2 .) 2. channelized mode refers to a da ta bit stream segmented into frames. each frame consists of a series of 8-bit time slots. the frame synchronization is maintained in bot h the transmit and receive direction by using the transmit synchronization (tsync) and receive synchronizati on (rsync) input signals. 3. an time slot bus (tsbus) (no ds0 extr action) is defined as 7 i nput/output signals as follows: transmit clock (tclk), transmit stuff (tstuff), transmit data (tdat), transmit strobe (tstb), receive clock (rclk), receive stuff (rstuff), receive data (rdat). (for a detaile d description of these signals, see chapter 4.0 ). 4. a time slot bus (tsbus) (with ds0 extrac tion) is defined as 9 input /output signals: transmit cl ock (tclk), transmit stuff (tstuff), transmit data (tdat), transm it strobe (tstb), receive clock (rclk), receive stuff (rstuff), receive data (rdat), receive group sync (rgs ync), transmit group sy nc (tgsync). for a detailed desc ription of these signals, see chapter 4.0 . table 1-1. supported cx28560 serial port modes (2 of 2) cx28560 serial port mode description table 1-2. allowed cx28560 port configurations speed of port 4 mbps 8 mbps 13 mbps 32.8 mbps 44.7 mbps 52 mbps number of ports 32 32 32 21 (1) 15 (1) 12 (1) note(s): (1) for high speed ports such as ds3 (44.736 mbps), e3 (34.368 mbps ), and hssi (52 mbps), the data path of the remaining ports may operate according to th e cx28560?s bandwidth restrictions.
1-4 mindspeed technologies? 28560-DSH-001-B advance information introduction cx28560 data sheet the cx28560?s configuration options are extremely flexible. each logical channel can be assigned to a physical stream ranging from a ds-0 (64 kbps) to 52 mbps. the cx28560?s serial ports can interface to a standard pcm highway or tsbus. examples of configurations are listed in table 1-4 . the send and receive data can be formatted in the hdlc messages or left unformatted (transparent mode) over any co mbination of bits within a selected time slot. the cx28560?s protocol message type is specified on a per-channel basis. table 1-3. data path configurations speed of port (mbps) low speed ports high speed ports aggregated port speed 4 8 10 13 32 44 52 allowed number of ports ???12??12780 (1) ? ? 7 ? ? ? 12 694 ? 9 ????12 696 19?????12 700 ? ? 17 ? ? 12 ? 698 ? 20 ? ? ? 12 ? 688 20 ? ? ? ? 12 ? 608 ? ? 20 ? 12 ? ? 584 ?20??12?? 544 20 ? ? ? 12 ? ? 464 table 1-4. examples of serial port configurations configuration total bit rate 15 x t3 671.040 mbps 21 x e3 688.128 mbps 12 x 52 + 12 x 12.96 (sonet) 622.080 mbps (1) 32 x 12*t1 592.896 mbps maximum 700 mbps note(s): (1) the guaranteed total bit rate of the chan nel (622.080 mbps) is lower than the aggr egate port rate (780 mhz). this is an example of a tsbus application where stuf fing would guarantee the bit rate to be within the maximum tolerated by the cx28560.
28560-DSH-001-B mindspeed technologies? 1 - 5 advance information cx28560 data sheet introduction 1.1.1.3 tsbus?time slot bus the cx28560 provides a tsbus interface for variable bandwidth time slots, virtual serial port (vsp). a vsp is defined as an entity?quantified by clock bus rate divided by number of time slots?which provides mu ltiple asynchronous paths over a single serial port. a programmable number of vsps per tsbus are allowed by using the existing start and end address time slot pointer mechanism. this mechanism allows the cx28560 to allocate any number of vsps on a given serial port. the total number of time slots allocated across all ports must not exceed 8192, the total number of logical channels must not exceed 2047, and the serial port clock speed must not exceed 52 mhz. while operating in tsbus mode, the minimu m number of time slots required is 5. the programmable number of time slots, im plemented by the pointer mechanism (i.e., configurable start and end addresses) allows any numb er of time slots to be concatenated into a single logical channel. this concatenation allows mixed vtg path options without changing the number of time slots assigned to the tsbus port. the stuff signal provides the cx28560 with the information n ecessary to pad time slots in the transmit direction, or to ignore them in the receive. when working in tsbus mode, ds0 signals can be extracted from a higher level (sonet/sdh/ds3 or e3) payload bit stream. this is performed in a similar manner to the tsbus frame mechanism, by using a group synchronizing pulse and a pointer mechanism. each group occupies fixed pl aces in the time slot map. when this position is reached, a group time slot map is consulted in order to retrieve the relevant channel number. (see appendix d for a detailed description).
1-6 mindspeed technologies? 28560-DSH-001-B advance information introduction cx28560 data sheet 1.2 system-side interfaces 1.2.1 pos-phy interfaces 1.2.1.1 pos-phy data interface?cx28560 data is transferred between the system and the cx28560 over a bidirectional standard pos-phy level 3 100 mhz, 32-bit interface, working in packet mode. the data is transferred as fragments accom panied by a 4-byte fragment header. data transferred on this pos-phy interface is in fragments of a user- configurable length (minimum 32 bytes, maximum 256 by tes) together with a fragment header (4 bytes). as the fragment length incr eases, the number of config urable channels decreases. when 56-byte fragments are used, up to 2047 channels may be configured; when 112- byte fragments are configured, a maximum of 1024 channels may be configured. see appendix i for an explanation of the relationshi p between fragment length, number of channels, and the channels? bandwidths. the last fragment of each message is marked as an end of message (eom) fragment. the next message starts with the fragmen t immediately following an eom fragment. the receive fragment header co ntains the following fields:  channel number  fragment length  end of message indicator  beginning of message indicator  message status the transmit fragment header contains the following fields:  channel number  command valid  idle code (ic) select (hdlc flags/aborts, all zeros) for padding between messages  pad count (padcnt) minimum number of idle codes to be inserted after message  abort command for fragment header formats see chapter 5.0 , pos-phy transactio n headers for full header layout.
28560-DSH-001-B mindspeed technologies? 1 - 7 advance information cx28560 data sheet introduction 1.2.1.2 transmit flowconductor interface the cx28560 provides the system with information necessary to calculate free buffer space available in the cx2856 0?s transmit buffers. this in formation is reported in packets of a specified format (see table 5-56, cx28560 flow conductor packet fo r m a t , transmitted over an 8-b it, 100 mhz, standard, leve l 3, unidirectional, pos- phy dedicated feedback interface. the format of the report is a counter based system whereby the system receives information re garding the amount of data transmitted since the previous report, and keeps track of the amount of space presently available in the channel?s transmit buffer. the pack ets received by the system contain the channel number, and the amount of space fr eed since the previous report for that channel was sent. (see appendix c for flow conductor interface). the system should be able to respond, if necessary, to the reports within 5 s. this interface may be fully utilized. see table 5-56, cx28560 flow conductor packet fo r m a t . 1.2.2 expansion bus (ebus) cx28560 provides an access to a local 32-b it bus interface called the expansion bus (ebus), which provides a host processor access to any address in the peripheral memory space on the ebus. although eb us use is optional, the most notable applications for ebus are connections to peripheral devices, such as bt8370/bt8398 t1/e1 framers, cx28398 (octal ds1/e1 framers), and cx29503/m29513 bam3/ bam3+ and cx29610 optiphy that are local to the cx28560?s serial port. the cx28560 provides access to the ebus through an interface similar to a mailbox interface. this interface provides all the ebus read and write accesses to be carried over the pci bus allowing bursts. this mechanism improves the pci use when multiple ebus accesses are needed for accessi ng the configuration of the peripheral devices. the ebus may be configured to use the intel- or motorola-style using a special bit in the ebus configuration register within th e host service unit (hsu). the ebus also supports slow devices by allowing the addr ess/data to be transferred over multiple cycles and thus allowing slow devices to read the address, access the data, or write it into their memories. 1.2.3 pci bus interface a standard pci 2.2 bus interface is provided to the system as an interface for configuring and reading the cx28560 registers, counters, and interrupts. the cx28560 acts as a pci master. conf iguration reads and writes and other commands are written by the system to the shared memory. these commands are retrieved via the cx28560?s hsu block, and passed internally to the relevant block to be performed. interrupts collated by the cx28560 are written to a user-configurable address in the shared memory for collection by the system.
1-8 mindspeed technologies? 28560-DSH-001-B advance information introduction cx28560 data sheet 1.3 feature summary the following is a summary of the features provided by the cx28560: 2047-channel, full-duplex link layer controller for synchronous applications. 32 full-duplex physical interfaces (i.e., ports) with independent clock rates. the cx28560 implements 32 serial ports that are individually programmable to operate either as conventional serial ports or tsbus serial ports. both operational modes allow the input/output data stream to be configured as channelized or unchannelized bit streams. clock rates may be as high as 52 mhz. general purpose hdlc (iso 3309) is supported. hdlc/sdlc hssi isdn d-channel (lapd/q.921) x.25 (lapb) frame relay (lapf/ansi t1.618) inter-system link protocol (islp) support lapdm support atm/smds dxi transparent unformatted mode point-to-point-protocol (ppp) multi-link-point-to-point-protocol (mlppp) hyper-channels and sub-channels are supported. applications that re quire hyper-channeling: ? isdn primary rate interface (pri) ? isdn primary rate adapter (pra) ? fractional t1 (ft1) ? fractional e1 (fe1) ? fractional nx64k ? sonet/sdh/pdh paths connected via tsbus: mixed vt1.5/vt2 paths mixed tu-11/tu-12 paths mixed t1/e1 paths ? multiple lines multiplexed to 1 port: digital subscriber line access multiplexer (dslam) t1/e1 frame relay sub-channeling mode ? each channel can be programmed to either use a complete ds-0 time slot or mask any subset of a time slot. a sign al mask is defined per-channel basis that has an enabled bit per time slot. the mask bit dictates whether the whole ds-0 or part of it is enabled. ? applications that re quire sub-channeling: isdn basic rate interface (bri) isdn basic rate adapter (bra) frame relay 56k and nx56k compressed voice transparent channels (e.g., adpcm) centralized signaling channel controllers: link access procedure d-channel (lapd)
28560-DSH-001-B mindspeed technologies? 1 - 9 advance information cx28560 data sheet introduction unchannelized mode applications that requ ire unchannelized ports: ? digital comm/termination equi pment (dce/dte) interfaces ? high speed serial interface (hssi) ? inter-process communication (ipc) ? v-series dte/dce interfaces (v.35) ? sdsl modems and access concentrators ? t3/e3 frame relay variable path primitives are supported. path payload ? ds-0 (64 kbps) ? nx64, where n is defined as any number between 1? 810, allows all types of hyper-channeling, channelized, unchannelized, or path payload higher speed ports ? unchannelized ds3 (44.736 mbps) ? unchannelized e3 (34.368 mbps) ? hssi (52 mbps) path overhead (performance monitoring and provisioning) ?t1/e1 ? facilities data link (fdl) ? common channel signaling (ccs) ? t3/e3 terminal data link (tdl) ? v.51 and v.52 signaling channels per-channel protocol selection is supported. non-fcs mode 16-bit fcs mode 32-bit fcs mode transparent mode dynamically configurable logical channels are supported. standard ds0 hyper-channel sub-channel programmable time slot allocation is supported. pointer mechanism per-channel buffc buffer management is supported. internal fifo of size 352 kb in the transmit di rection and 320 kb in the receive direction. one size of channel fifo required rega rdless of channel bi t rate (allows for dynamic reconfiguration of specific channels without full chip reset) configurable buffc threshold set on a per-channel basis in the transmit direction programmable fifo size per-chip basis clear to send (cts) per-channel control of data transmission in conventional mode ports. direct pos-phy bus interface is supported. pci bus interface (rev. 2.2) for configuration purposes only. 32-bit multiplexed address/data bus minimizes pin count 33 mhz operation
1-10 mindspeed technologies? 28560-DSH-001-B advance information introduction cx28560 data sheet ebus?expansion bus interface is provided. 32-bit multiplexed address/data allows host to control other local devices facilitates host access to any local memory tsbus interface. variable bandwidth time slot ds0 level extraction and synchronization multiple asynchronous paths over single port allows sonet/sdh/pdh paths connection ? mixed vt1.5/vt2 paths ? mixed tu-11/tu-12 paths ? mixed t1/e1 paths full set of performance monitoring counters provided receive direction: ?octets ?packets ? packets with alignment errors ? packets with too short errors ? packets with too long errors ? packets with fcs errors ? packets terminating in an abort transmit direction: ?octets ?packets ? packets transmitted terminating in an abort signal 3.3 v/1.8 v supply; 5 v-tolerant inputs jtag access is provided low power cmos technology is used 1 a at 1.8 v, 0.34 a at 3.3 v (accordin g to preliminary mini-characterization)
28560-DSH-001-B mindspeed technologies? 1 - 11 advance information cx28560 data sheet introduction 1.4 applications examples figure 1-1. oc-12 application 100989_003 cx29610 (oc-12 multiplexer) cx28560 sibus ebus pci cx29503 cx29503 bam-3 cx29503 cx29503 tsbus tsp pos-phy sibus tsbus sibus tsbus sibus tsbus host processor pci bridge note(s): tsbus time slot bus?mindspeed proprietary bus. sibus serial interface bus?mindspeed proprietary bus. tsp traffic stream processor. optiphy m622
1-12 mindspeed technologies? 28560-DSH-001-B advance information introduction cx28560 data sheet 1.5 system overview cx28560 supports 32 fully independent serial ports that can be configured to run in channelized, unchannelized, t1 or tsbus (with or without ds0 extraction) mode. for example, in the channelized mode, the fi rst 12 ports can operate up to 51.81 mbps (sts-1 rate) while the another 20 ports can operate up to 12.96 mbps (maximum sonet overhead rate). each sts-1 frame transports 28xt1, 1xt3, 21xe1 or mixed t1/e1 vtg paths, while the overhead bit st reams contain the over head required. the configuration is valid as long as the overal l number of time slots per the whole device is 8192 time slots or less. for other restrictions see section 1.1.1.2 . alternatively, any of the cx28560?s ports can interface unchannelized data streams (hdlc or unformatted). in this mode, ea ch of the first twelve ports can be configured to operate up to 52 mbps. the restriction is that the overall data bandwidth must not exceed 700 mbps (full duplex). the cx28560 manages uniformly allocated buffer memory according to the flexiframe algorithm for each of the act ive data channel, allowing the user to reconfigure any channel without affecting ot her active channels. the on- device features allow data transmission between buffer memory and the serial interfaces with minimum host processor inte rvention. this allows the host processor to concentrate on managing the high er layers of the protocol stack. figure 1-2. system overview 101302_001 jtag host processor shared memory local host optional components local bus pci bus ebus local memory local bus pci bridge pcm highway or tsbus serial interface 0 physical interface 0 physical interface 1 physical interface 31 serial interface unit serial interface 31 processing blocks pos- phy interface pci interface ebus interface
28560-DSH-001-B mindspeed technologies? 1 - 13 advance information cx28560 data sheet introduction the tsbus interface provides multiple asyn chronous paths (all tsbus frames run at 51.84 mbps). the supported tsbus framer configurations that are mapped into and from vsps are as follows:  there are 28 pdh framers and 28 sonet/sdh framers. either of these two categories of framers can be mapped directly to the vsps for a given configuration.  when using the pdh framers, each frame r can be independently configured as a ds1 framer or as an e1 framer.  the sonet/sdh category of framers has two subcategories as the name implies. when using the sonet/sdh frame rs, they all have to be configured as either sonet framers (one subcateg ory) or as sdh framers (the other subcategory). the configurations of the sonet/sdh framers when configuring for sonet subcategory of framers, each framer can be independently configured as a vt1.5 framer or as a vt2.0 framer. the sdh subcategory of framers is similarly configured. each sdh framer can be independently configured as either a c11 framer or an e1 framer. the supported tsbus frame structures are ds0s, ds1s, e1s mapped via ds2, vt1.5, vt2.0, c11, and c12. the following mixed mappings are also su pported by selectively configuring each framer:  ds0s extracted from mixed ds1s via the tsbus  ds1s and e1s extracted from mixed ds2s via the pdh framers  ds1s and e1s extracted from mi xed vtgs via the sonet framers  c11s and c12s extracted from mixed tug-2s via the sdh framers the frame structure is de signed to transport the  unchannelized sts-1 synchronous payload envelope (spe)  unchannelized ds3 payload  16 e1 signals that are mapped to and from e3
1-14 mindspeed technologies? 28560-DSH-001-B advance information introduction cx28560 data sheet 1.6 block diagram figure 1-3 illustrates the cx28560 conceptual block diagram. figure 1-3. cx28560 block diagram 101302_003 expansion bus interface (ebus) 32 buffer controllers ( rbuffc & tbuffc) receive serial line processor (rslp) transmit serial line processor (tslp) test access data stream data stream data dwords data dwords data bytes data bytes 8 8 32 32 receive serial interface unit (rsiu) transmit serial interface unit (tsiu) serial ports 0 ? 11 serial ports 12 ? 31 rclkn tclkn rsyncn(rstuffn) tsyncn(tstuffn) roofn/tctsn(tstbn) rdatn rgsyncn tgsyncn tdatn rclkn tclkn rsyncn(rstuffn) tsyncn(tstuffn) roofn/tctsn(tstbn) rdatn tdatn 7 2 6 pci interface host pos- phy interface 32 32 2 2 8 32 4 jtag tdi tck tms tdo ten 4 4 tfclk onesec terr tenb tdat[31:0] tmod[1:0] tsop teop ptpa tprty rfclk rval renb rdat[31:0] rmod[1:0] rsop reop rclav rprty frfclk frval frenb frdat[7:0] frsop freop frprty frprty frclav ad[31:0] cbe[3:0] par frame trdy irdy stop devsel idsel perr gnt inta prst pclk ead[31:0] ebe[3:0] ale wr(r/wr) rd(ds) eclk hold(br) hlda(bg) bgack req serr test mode
28560-DSH-001-B mindspeed technologies? 1 - 15 advance information cx28560 data sheet introduction the following is a description of the block diagram.  host interface (pos-phy): this block pr ovides the communication path of the data between the host and the cx28560.  pci host interface: this block interfa ces to the pci bus over which the host configures and monitors the cx28560 action.  expansion bus (ebus): the ebus is an extension of the pci host interface, which provides host with access to contro l other devices on the local pc board.  serial interface unit (siu): this block provides the interface between 32 serial ports and the receive and transmit serial line processors block. a temporal buffering space is provided by the siu that is 56 bits per port, divided as 32 bits (4 bytes) for the transmit direction and 24 bi ts (3 bytes) for the receive direction. siu controls the data access to the rx an d tx serial line processors. because the cx28560 supports two types of serial ports?one is the conventional interface, the other tsbus interface?the siu needs to operate depending on serial port type (for detailed descriptor information, see chapter 4.0 ).  transmit serial line processor (tslp): this block provides the interface between the buffer controller (buffc) and the tsiu. data provided by the buffc is processed by the tslp according to the channel type and passed to the tsiu for transmission to the line.  receive serial line processor (rslp): this block provides the interface between the siu and buffc. the data provided by rsiu is processed by rslp according to the channel type before it is transferred to the buffc.  buffc: this block provides the interf ace between the host and the transmit and receive serial line processors (tslp and rslp). the buffc contains the main storage of data?a dual port ra m of 352 kb in the transmit direction and 320 kb in the receive direction. th is space acts as a holding buffer for incoming (rx) and outgoing (tx) data.  jtag: this is a special test port used for serial boundary scan on a pcb, as well as access to internal scan paths and embedded memory for test.  onesec: the onesec signal provides the boundaries on which the performance monitoring counters are latched.
1-16 mindspeed technologies? 28560-DSH-001-B advance information introduction cx28560 data sheet 1.7 data flow 1.7.1 receive data path data enters the cx28560 vi a 32 independently configurable ports. within the cx28560 data is processed to remove hdlc formatting and to perform message error detection (e.g., fcs error, alignment error, etc.), and concatenated to fixed length chunks (of user-configurable length) that are then transferred to the system. the internal memory required per channel in the cx28560 is constant, regardless of the channel?s rate. this is achievable due to the flexiframe algorithm (see appendix b ). the flexiframe method provides a fixe d order (frame) for servicing the cx28560 channel internal buffers. the frame structur e allocates service time to each channel proportionally to its bit rate. the cx28560 runs through the frame and decides whether or not the next channel in the frame requires servicing (i.e., whether it contains an eom or enough data to fill a standard fragment). if so, the data is passed to the pos-phy interface and is transmitted to the system. 1.7.2 transmit data path the system stores the data un til a report is received from the cx28560 via the flow conductor bus. on receiving the report, the system calculates whether or not there is room in the channel?s cx28560 internal bu ffer. if so, data is transferred to the cx28560 in complete packets over the 32 bit pos-phy interface. the cx28560 processes the data receiv ed and outputs hdlc formatted data. according to the flexiframe algorithm, reports of the amount of buffer freed are sent to the system over the dedicated 8-bit unidirectional fl ow conductor bus. according to the reports received, the system provides fixed size fragments of data over the 32-bit bidirectional pos-phy bus. see appendix b and appendix c for more details. formatted, masked, and time slot ordered data is transmitted to the line from the cx28560 via 32 independently configurable ports.
28560-DSH-001-B mindspeed technologies? 1 - 17 advance information cx28560 data sheet introduction 1.8 cx28560 pin list 1.8.1 pin descriptions table 1-5 lists the pin summary. table 1-5. pin summary interface in out i/o total table serial 20 6 20 1 0 140 table 1-6, serial interface (general) tsbus (ds0) 12 7 12 2 0 108 table 1-7, with ds0 extraction mode addi tional pins (12 ports only) pos-phy transmit 40 1 0 41 table 1-8, cx28560 pos-phy interface (transmit) pos-phy receive 2 39 0 41 table 1-9, cx28560 pos-phy interface (receive) pos-phy flowconductor 2 13 0 15 table 1-9, cx28560 pos-phy interface (receive) pci 4 0 46 50 table 1-10, pci interface ebus 1 10 32 43 table 1-11, ebus interface (communication with peripheral components) jtag 4105 table 1-12, boundary scan and test access test 4 0 0 4 table 1-12, boundary scan and test access onesec 1 0 0 1 table 1-13, performance monitoring total 262 108 78 448 ? note(s): the serr and inta signals are i ndicated above as output pins. they are implemented as i/o cells due to design considerations.
1-18 mindspeed technologies? 28560-DSH-001-B advance information introduction cx28560 data sheet table 1-6 lists pins common to all ports. table 1-6. serial interface (general) (1 of 3) pin name i/o ref clk description tclk[31:0] i ? transmit clock (tclk[31:0]. if the se rial port is configured in conventional mode, tclkx controls the rate at which data is transmitted a nd synchronizes transitions for tdatx and sampling of tsyn cx. if the port is configur ed as a tsbus port, tclkx controls the rate at which data is transm itted and synchronizes transitions for tdatx and sampling of tstuffx and tstbx (tstbx only for transmit circuitry). if in tsbus with ds0 extr action mode in addition to the above, tclkx also synchronizes transitions of tgsyncx. tsync[31:0]/ tstuff[31:0] i tclk[31:0] transmit synchronizati on/tsbus transmit stuff (tsyncx [31:0]/tstuff[31:0]). if the serial port is configured in conventional mode, this signal is defined as tsyncx. tsyncx is sampled on the specified acti ve edge of the corre sponding tclkx clock. when tsyncx signal goes from low to high, the start of transmit frame is indicated. tsyncx is ignored if the serial port is configured to operate in conventional unchannelized mode. if the serial port is configured in t1 mode, the corresponding data bit that latched out duri ng the same bit time period ( but not necessar ily sampled at the same clock edge) is the f-bit of the t1 fr ame. if the serial port is configured in conventional channelized m ode, the corresponding data bit that latched out during the same bit time period (but not necessarily sampled at the same clock edge) is bit 0 of the first time slot of the n.... 64 frame. because the cx28560?s flywheel mechanism is always used in channelized mode, no other synchronization signal is required to tr ack the start of each subsequent frame. if the port is configured to operate as tsbu s port, this signal is defined as tstuff. the tstuff values are to either stuff (no tdat output) or not stuff (tda t valid). tstuff is sampled on the specified active edge of the corresponding tclkx. if the serial port operates in tsbus mode, ts tuff assertion indicates th at no data needs to be transmitted in the 8 th time slot after the as sertion of the tstuff. while operating in tsbus mode, th e cx28560 requires the following: the stuff status for each time slot to be presented at its ts tuff input exac tly eight time slots in advance of the actual time slot for which the stuff status is to be applied. the amount of the tstuff advance is fixed at eight time slots, even though the number of time slots within a frame may vary. the cx28560 expects assert ion of this signal within the fi rst two bits of the time slot. assertion of this signal elsewh ere in the time slot might re sult in undefined behavior. tdat[31:0] o tclk[31:0] transmit data (tdat[31:0]) serial data latched out on active edge of transmit clock, tclkx. if channel is unmappe d to time slot, data bit is considered invalid and the cx28560 outputs either three- state signal or logic 1 (user-configurable, see table 5- 53, tsiu port configuration register , field tritx).
28560-DSH-001-B mindspeed technologies? 1 - 19 advance information cx28560 data sheet introduction roof[31:0]/ cts [31:0]/ tstb[31:0] i tclk[31:0]/ rclk[31:0] this pin has three separate defi nitions. control of the use of the pin is configured in the table 5-39, rsiu port configuration register and table 5-53, tsiu port configuration register using the ctsenb and roofabt fields. (2)(3)(5) receiver out-of-frame roof[31:0]. if the pi n is configured to be roofx, it is sampled on the configured ac tive edge of the correspondi ng receive cloc k rclkx. if roofx signal performs a transition from lo w to high (assertion), an out-of-frame (oof) condition interrupt is ge nerated if the interrupt is enabled. while roofx is asserted, the received serial data stream is considered out-of-frame. if oofabt bit field is configured to 1, the receive channe l processing is disabled for the entire port and it remains disabled until roofx is de asserted; otherwise, the receive channel processing is enabled. upon ro ofx deassertion, if oofien bit field is set to 1, an interrupt frame recovery (frec) is genera ted. the data proces sing resumes for all affected channels. general interrupt line. this sign al can also operate as a general serial port interrupt (sport) by clearing the oofabt bit field a nd setting the oofien bi t field (i.e., oofabt = 0 and oofien = 1). when the roofx signal transitions from high-to-low (deassertion), a sport interrupt is generated and data stream is not affected. if this signal is used as a general pur pose interrupt, no interrupt is generated until this signal goes from high to low. (2)(3)(5) channel clear to send (cts[31:0]). if ctsx, the signal is sampled on the specified active edge of th e corresponding transmit clock, tclkx. if cts transitions from high-to-low (is deasserted), the ch annel assigned to the time slot sends continuous idle characters af ter the current message has been completely transmitted. the message transmission data restarts when this cts transitions from low to high again (is asserted). the response time to cts is a 32 bit-time, meaning that a new message might be transmitted if the message starts within the next 32 bits after cts was deasserted. (2)(4)(5) tsbus strobe (tstb[31:0]) if the port is configured in tsbus mode the this pin is used as tstbx. the signal is sample d twice, once by the receive circuitry on the specified edge of the corresponding receive clock, rclkx, and once by the transmit circuitry on the specified edge of th e corresponding transmit clock, tclkx. if tstb transitions from low to high, it ma rks the first bit of time slot 0 within the tsbus frame. because there is a single tstb for both directions, receive and transmit, the number of configured time slots and the rport_type or tport_type value specifying whether the serial port operate s in tsbus or non-tsbus mode must be identically configured for both directions per serial port. unexpected cx28560 behavior may be generated if this restriction is violated. rclk[31:0] i ? receive clock (rclk[31:0 ]). this clock controls the rate at which data is received and synchronizes sampling of rdatx, rsyncx (non-tsbus mode onl y), rstuffx (tsbus mode only), and tstbx (tsbus mode only, and only for receive path circuitry). if in tsbus (with ds0 extraction) mode, rclkx also synchronizes transitions of rgsyncx. table 1-6. serial interface (general) (2 of 3) pin name i/o ref clk description
1-20 mindspeed technologies? 28560-DSH-001-B advance information introduction cx28560 data sheet rsync[31:0]/ rstuff[31:0] i rclk[31:0] receive synchronizati on/receive stuff (rsy nc[31:0]/ rstuff[31: 0]). if the port operates in a conventional mode, this signa l is defined as rsync. rsync is sampled on the configured active e dge of the corresponding receive clock, rclkx. rsyncx is ignored if the serial por t is configured to opera te in unchannelized mode. if rsyncx signal transitions from low to high, the start of a receive frame is indicated. for t1 mode, the corresponding sa mpled and stored data bit during the same bit-time period (not necessarily samp led on the same clock edge) is the f-bit. for the conventional channelized m ode, the corresponding data bit sampled and stored during the same bit time period (not necessarily sa mpled on the same clock edge) is bit 0 of the first time slot of the n.... 64 frame. rsyncx must remain asserted high for a mi nimum of pci setup and hold time relative to the active clock edge of this signal. since the cx28560?s flywheel mechanism is always used in channelized mode, no other synchronization signal is required to track the start of each subsequent frame. if the port operates as a tsbus port, this signal is rstuff. the rstuff is sampled on the configured active edge of the corresponding rclkx. in this case, rstuff assertion indicates that this time slot contains no data. while operating in channelized mode, the cx28560 expects assert ion of this signal within the first two bits of the time slot. as sertion of this signal elsewhere in the time slot might result in undefined behavior. rdat[31:0] i rclk[31:0] receive data (rda t[31:0]) serial data samp led on active edge of receive clock, rclkx. if the channel is mapped to a time slot, i nput bit is sampled and transferred to memory. if the channel is unmapped to time slot, data bit is c onsidered invalid and the cx28560 ignores the received sample. note(s): 1. while operating in tsbus mode, there is no damage expected when sa mpling tstbx twice, because the rclkx and tclkx are the same signals for a specific port. however, this may require some additional restrictions for the board designers when these clocks are routed. 2. this signal is used either as receiver out-of-frame or a transmit clear to se nd or a tsbus strobe. (oof/frec behavior selected by oofabt = 1, cts behavior selected by ctsenb = 1, tstb behavior selected by tpor t_type or rport_type). 3. if the serial port operates in conventional mode, this signal is used either as a roofx or ctsx signal. 4. if the port operates in ds0 extr action mode, the signal is used as the tsbus strobe signal, wh ich indicates the beginning of the tsbus frame. 5. only one pin in the device defines all th ese functions. table 1-6. serial interface (general) (3 of 3) pin name i/o ref clk description
28560-DSH-001-B mindspeed technologies? 1 - 21 advance information cx28560 data sheet introduction table 1-8 describes data transfer fro m the system to the cx28560. table 1-7. with ds0 extraction mode additional pins (12 ports only) pin name i/o ref clk description tgsync[11:0] o tclk[11:0] payload time slot bus transmit ds0 sync (tgsync). when high, indicates that data on tdata is the first bit of the fi rst group configured for the port of ds0 valid data. rgsync[11:0] i rclk[11:0] payload time slot bus receive ds0 sync (rgsyn c). when high, indicates that data on rdata is the first bit of the fi rst group configured for the port of ds0 valid data. table 1-8. cx28560 pos-phy interface (transmit) (1 of 2) pin name i/o ref clk description tfclk i ? transmit fifo write cloc k. tfclk synchronizes data tran sfer transactions between the system and the cx28560. tfclk cycles at a ra te of 100 mhz. other signals are sampled on the rising edge of this signal. terr i tfclk transmit error indicato r signal. terr indicates that the current packet should be aborted. when terr is set high, the current packet is aborted. terr should only be asserted when teop is asserted. tenb i tfclk transmit write enable (ten b) signal. the tenb signal contro ls the flow of data to the transmit fifos. when tenb is high, th e tdat, tmod, tsop, teo p, and terr signals are invalid and are ignored by the cx28560. wh en tenb is low, the tdat, tmod, tsop, teop, and terr signals are valid and are processed by the cx28560. tdat[31:0] i tfclk transmit packet da ta bus. this bus carries the packet octets that are written to the cx28560?s fifo. the tdat bus is considered valid only when tenb is asserted. data must be transmitted in big endian order on tdat[31:0]. in accordance with the hdlc protocol, bit 0 of each by te is transmitted first. tmod[1:0] i tfclk transmit word modulo signal. tmod[1:0] indi cates the number of valid bytes of data in tdat[31:0]. the tmod[1:0] bus should always be all zero, except during the last double-word transfer of a packet on tdat[ 31:0]. when teop is asserted, the number of valid packet data by tes on tdat[31:0] is sp ecified by tmod[1:0]. tmod[1:0] = 00 tdat[31:0] valid tmod[1:0] = 01 tdat[31:8] valid tmod[1:0] = 10 tdat[31:16] valid tmod[1:0] = 11 tdat[31:24] valid tsop i tfclk transmit start of packet (tsop) sign al. tsop delineates the packet boundaries on the tdat bus. when tsop is high, the start of the packet is present on the tdat bus. tsop must be present at the beginning of every pa cket and is considered valid only when tenb is asserted. teop i tfclk transmit end of packet (teop) signal. teop delineates the pa cket boundaries on the tdat bus. when teop is high, the end of the packet is pres ent on the tdat bus. tmod[1:0] indicates the numbe r of valid bytes the last double word is composed of when teop is asserted. teop must be pres ent at the end of every packet and is considered valid only when tenb is asserted.
1-22 mindspeed technologies? 28560-DSH-001-B advance information introduction cx28560 data sheet ptpa o tfclk transmit packet available (ptpa) si gnal. ptpa transitions high when a predefined minimum number of bytes are available in the polled transm it fifo. once high, ptpa indicates that the transmit fifo is not full. when ptpa transitions low, it optionally indicates that the transmit fifo is full or near full. ptpa allows the polling of the cx28560. the port which ptpa reports is updated on the following rising edge of tfclk. ptpa is updated on th e rising edge of tfclk. tprty i tfclk transmit bus pa rity signal (tprty). tprty indicate s the parity calculated over the tdat bus. tprty is considered valid only when tenb is asserted. the cx28560 supports odd parity checking which can be disa bled by configuring the disblpar bit in the table 5-21, transmit pos-phy th resholds register .the cx28560 reports any parity error to the system, but shall not interfere with the transferred data. note(s): the following pins are supported by the st andard pos-phy, but are no t required because the cx28560 supports only packet-level transfers on a single phy basis: transmit start of transfer (tsx) signal; transmit phy addr ess (tadr[]) bus; direct transmit packet available (dtpa[]); selected-phy transmit packet available (stpa) signal. table 1-8. cx28560 pos-phy interface (transmit) (2 of 2) pin name i/o ref clk description
28560-DSH-001-B mindspeed technologies? 1 - 23 advance information cx28560 data sheet introduction table 1-9 describes data transfer from the cx28560 to the system. this covers two interfaces?the data interface (32 bit, 10 0 mhz) and the flowconductor interface (8 bit, 100 mhz). table 1-9. cx28560 pos-phy interface (receive) (1 of 2) pin name i/o ref clk description rfclk frfclk i ? system to the cx28560 receive fifo wri te clock (rfclk). rfclk is used to synchronize data transfer transactions between the sy stem and the cx28560. both rfclk and frfclk cycle at 100 mhz and si gnals are sampled on their rising edges. rval frval orfclk frfclk receive data valid (rval) signal. rval indicates the validity of the receive data signals. rval will transition low when a receive fifo is empty or at the end of a packet. when rval is high, the rdat[31:0], rprty, rmod[1:0], rsop, and reop signals are valid. when rval is low, th e rdat[31:0], rprty, rmod[1:0], rsop, and reop signals are invalid and must be disregarded. frval indicates the validity of the receiv e data signals. frval will transition low when a receive fifo is empty or at the end of a packet. when frval is high, the frdat[7:0], frprty, frsop, and freop signals are valid. when frval is low, the frdat[7:0], frprty, frsop, and freo p signals are invalid and must be disregarded. renb frenb irfclk frfclk receive read enable (renb) signal. the renb signal controls the flow of data from the receive fifo?s. during data transfer, rval must be monitored as it will indicate if the rdat[31:0], rprty, rmod[1:0], rsop, and reop are valid. the system may deassert renb at anytime if it is unable to accept data from the cx28560. when renb is sampled low by the cx28560, a read is performed from the rece ive fifo and the rdat[31:0], rprty, rmod[1:0], rsop, reop, and rval signals are updated on the following rising edge of rf clk. when renb is sampled high by the cx28560, a read is not perf ormed, and the rdat[31:0], rprty, rmod[1:0], rsop, reop, and rval signals will not updated on the following rising edge of rfclk. the frenb signal is used to control the flow of data from the receive fifo?s. during data transfer, frval must be monitored as it will indicate if the frdat[7:0], frprty, frsop, and freop are valid. the system may deassert frenb at anytime if it is unable to accept data from the cx28560. when frenb is sampled low by the cx28560, a read is performed from the re ceive fifo and the frdat[7:0], frprty, frsop, freop, and frval signals are updated on the following rising edge of frfclk. when frenb is sampled low by the cx28560, a read is not performed and the frdat[7:0], frprty, frsop, freop, an d frval signals will not updated on the following rising edge of frfclk. rdat[31:0] frdat[7:0] orfclk frfclk receive packet data bus (rdat[31:0] for data interface, frdat[7:0] for flowconductor interface). the rdat[31:0] /frdat[7:0] bus ca rries the packet octets that are read from the receive fifo and the in-band port address of the selected receive fifo. rdat[31:0]/frdat[7:0] is considered valid only when rval/ frval is asserted on the 32-bit interface; data must be rece ived in big endian order. in accordance with hdlc protocol, bit 0 of ea ch byte is the first received bit at the serial interface.
1-24 mindspeed technologies? 28560-DSH-001-B advance information introduction cx28560 data sheet rmod[1:0] o rfclk receive word m odulo (rmod) signal. rmod[1:0] indicates the num ber of valid bytes of data in rdat[31: 0]. the rmod bus should al ways be all zero, except during the last double-word transfer of a packet on rdat[31:0]. when reop is asserted, the number of valid packet da ta bytes on rdat[31:0] is specified by rmod[1:0]: rmod[1:0] = 00 rdat[31:0] valid rmod[1:0] = 01 rdat[31:8] valid rmod[1:0] = 10 rdat[31:16] valid rmod[1:0] = 11 rdat[31:24] valid when the flowconductor 8-bit interface, the rmod bus is not considered. rmod[1:0] is considered valid only when rval is asserted rsop frsop orfclk frfclk receive start of packet (rsop/frsop) signal. rsop/frsop delineates the packet boundaries on the rdat/frdat bus. when rs op/frsop is high, the start of the packet is present on the rd at/frdat bus. rsop/frsop wi ll be present at the end of every packet and is considered valid when rval/frval is asserted. reop freop orfclk frfclk receive end of packet (reo p/freop) signal. reop/freop delineates the packet boundaries on the rdat/frdat bus. when re op/freop is high, the end of the packet is present on the rd at/frdat bus. on the data 32-bit interface, rmod[1:0] indicates the number of valid bytes the la st double word is composed of when reop is asserted. on the flowconductor 8-bit interf ace, the last byte of the packet is on frdat[7:0] when freop is as serted. reop/freop is requi red to be present at the end of every packet and is considered valid only when rval/frval is asserted. rprty frprty orfclk frfclk receive parity (rprty/frprt y) signal. the receive pari ty (rprty/frprty) signal indicates the parity calcul ated over the rdat/frdat bus. on the flowconductor 8- bit interface, the cx28560 only supports fr prty calculated ov er frdat[7:0]. the cx28560 supports parity calculation. rclav frclav orfclk frfclk receive cell available (rclav/frclav). rclav/frclav indicates when the system device has data to transfer. this si gnal is only relevant in registered mode (see chapter 2.0 ). note(s): 1. the receive start of transfer (rsx) pin is supported by the standard po s-phy, but are not re quired because the cx28560 supports only packet-level tr ansfers on a single phy basis. 2. the cx28560 architecture guarantees that the rerr pin, if impl emented, would never be assert ed. therefore, to comply fully with pos-phy, the system should tie rerr to zero. table 1-9. cx28560 pos-phy interface (receive) (2 of 2) pin name i/o ref clk description
28560-DSH-001-B mindspeed technologies? 1 - 25 advance information cx28560 data sheet introduction table 1-10. pci interface (1 of 2) pin name i/o ref clk description pclk i ? pci clock (pclk). pclk provides timi ng for all pci transitions. all pci signals except prst*, inta*, a nd intb* are synchronous to pclk and are sampled on the rising edge of pclk. the cx28560 supports a pci clock up to 33 mhz. ad[31:0] i/o pclk pci address and data (ad[31:0]). ad[31:0] is a mu ltiplexed address/data bus. a pci transaction consists of an address phase duri ng the first clock period followed by one or more data phases. ad[7 :0] is the lsb. as both a master and a target, the cx28560 supports only 32-bit operations. cbe[3:0] i/o pclk pci command and byte enables (c be[3:0]). during the ad dress phase, cbe[3:0] contain command information. during the data phases, cbe[3:0] contain information denoting whic h byte lanes are valid. supported pci commands are defined as follows: cbe[3:0] command type 6h 0110b 7h 0111b ah 1010b bh 1011b ch 1100b eh 1110b fh 1111b memory read memory write configuration read (target only) configuration write (target only) memory read multiple memory read line memory write and invalidate (target only) par i/o pclk pci parity (par). the number of 1s on par, ad[31:0], and cbe[3:0] is an even number. par always lags ad[31:0] an d cbe* by one clock. during address phases, par is stable and valid one cl ock after the addres s; during the data phases, it is stable and valid one clock after trdy on reads and one clock after irdy on writes. it remains valid until one clock after th e completion of the data phase. frame i/o pclk pci frame (frame). frame is driv en by the current master to indicate the beginning and duration of a bus cycle. da ta cycles continue as frame stays asserted. the final da ta cycle is indicated by the deassertion of frame. for a non-burst, one-data-cycle bus cycle, this pin is only asserted for the address phase. trdy i/o pclk pci target ready (trdy). asserted indicates the target?s readiness to complete the current data phase. irdy i/o pclk pci initiator ready (irdy). asserted indicates the current master?s readiness to complete the current data phase. stop i/o pclk pci stop (stop). asserted indicates the selected target is requesting the master to stop the current transaction. devsel i/o pclk pci device select (devsel). asse rted indicates that th e driving device has decoded its address as the target of the current cycle. idsel i pclk pci initializa tion device select (idsel). this input is used to select the cx28560 as the target for configuration read or write cycles.
1-26 mindspeed technologies? 28560-DSH-001-B advance information introduction cx28560 data sheet perr i/o pclk parity error (perr). perr* is asserted by the agent receiving data when it detects a parity error on a data phase. it is asserted one clock after par is driven, which is two clocks after the ad and cbe pari ty was checked. if the cx28560 masters a pci write cycle, and?after supplying the data during the data phase of the cycle?detects th is signal being asserted by the agent receiving the data, then the cx 28560 generates a perr interrupt. if cx28560 masters a pci read cycle, and?after receiv ing the data during the data phase of the cycle?ca lculates that a parity e rror has occurred, the cx28560 asserts this signal and also generates th e perr interrupt descriptor towards the host. serr o pclk system error (serr). any pci device ca n assert serr to indicate a parity error on the address cycle or parity error on the data cycle of a special cycle command or any other system error where the result will be catastrophic. the cx28560 asserts serr if it detect s a parity error on the addr ess cycle or encounters an abort condition while operating as a pci ma ster. since serr is not a sustained three-state signal, restoring it to the dea sserted state is done with a weak pull-up (same value as used for sustained three state) (1) . req i/o pclk pci bus request (req). the cx28560 drives req to notify the pci arbiter that it desires to master the bus. every master in the system has its own req. gnt i pclk pci bus grant (gnt). the pci bus ar biter asserts gnt when the cx28560 is free to take control of the bus, assert frame, and execute a bus cycle. every master in the system has its own gnt. inta o pclk pci cx28560 interrupt (inta). inta is driven by the cx28560 to indicate a layer 2 interrupt condition to the host processor. prst i none pci reset (prst). this input resets all functions on the cx28560. note(s): (1) the cx28560 does not input serr. it is assu med that the host will reset cx28560 in th e case of a catastrophic system error. table 1-10. pci interface (2 of 2) pin name i/o ref clk description
28560-DSH-001-B mindspeed technologies? 1 - 27 advance information cx28560 data sheet introduction table 1-11. ebus interface (communication with peripheral components) pin name i/o ref clk description eclk o ? expansion bus clock (eclk). the eclk bi t field is an inverted version of the pci clock. ead[31:0] i/o eclk expansion bus a ddress and data (ead[31:0]). ead[31:0] is a multiplexed address/data bus. ebe[3:0] o eclk expansion bus byte enables (ebe[3 :0]). ebe contains byte -enabled information for the ebus transaction. ale (as) o eclk address latch ena ble (ale (as)). high-to-low transition indicates that ead[31:0] bus contains valid address. remains asserted low through the data phase of the ebus access. (in motorola mode, high-to-low transition indicates ebus contains a valid address. remains asserted for the entire access cycle.) wr (r/wr) o eclk write strobe (wr (r/wr)). high-to-low transi tion enables write data from cx28560 into peripheral de vice. rising edge define s write. (in motorola . mode, r/wr is held high throughout read and held low throughout write. determines meaning of ds strobe.) rd (ds) o eclk read strobe (rd (ds)). high-to-low transition enables read data from peripheral into cx28560. held high throughout write operation. (in motorola mode, ds transitions low for both read and write operations and is held low throughout the operation.) hold (br) o eclk hold request (bus request) (h old (br)). when asserted, cx28560 requests control of the ebus. hlda (bg*) i eclk hold acknowle dge (bus grant) (h lda (bg)). when asserted, cx28560 has access to the ebus. it is held asserted when there are no other masters connected to the bus, or asserted as a handshake mechanis m to control ebus arbitration. bgack o eclk bus grant acknowledge (bgack). wh en asserted, cx28560 acknowledges to the bus arbiter that the bus grant signal was de tected and a bus cycl e is sustained by cx28560 until this sign al is de-asserted.
1-28 mindspeed technologies? 28560-DSH-001-B advance information introduction cx28560 data sheet table 1-12. boundary scan and test access pin name i/o ref clk description tck i ? jtag clock (tck). used to clock in the tdi and tms signals and as clock out tdo signal. trst i tck jtag enable (trst). an active-low input used to put the chip into a special test mode. this pin should be pulled up in normal operation. tms i tck jtag mode select (tms ). the test signal input dec oded by the tap controller to control test operations. tdo o tck jtag data output (tdo) the test signal used to transmit serial test instructions and test data. tdi i tck tdi jtag data input (tdi ) the test signal used to recei ve serial test instructions and test data. tm[3:0] i ? test mode (tm). encodes tests mode s (must be pulled low in normal operation). table 1-13. performance monitoring pin name i/o ref clk description onesec i ? an asynchronous pulse provided as an input to cx28560 that causes the latching of the performance monitoring count ers. not necessarily on one-second boundaries.
28560-DSH-001-B mindspeed technologies? 2 - 1 advance information 2.0 host interfaces 2.1 host interface the cx28560?s host interface consists of a pci interface, a pos-phy data interface and a pos-phy flow conductor interface. over these interfaces the following major func tions are performed:  transfer of data as fragments between the cx28560 and the system;  configuration and monitoring of the cx28560 registers and counters;  monitoring the fill level of the cx 28560?s internal per channel buffers.
2-2 mindspeed technologies? 28560-DSH-001-B advance information host interfaces cx28560 data sheet figure 2-1 illustrates the cx28560 host interface block diagram. figure 2-1. the cx28560 host interface functional block diagram 101302_029 pci bus (33 mhz, 32 bit) device configuration registers host interface unit pci interface pci configuration space data pos-phy interface flowconductor pos-phy interface clock control data interrupt interrupts tx control rx control tx data rx data tx flow control processing blocks clock tx data rx data tx flow control clock bi-directional data pos-phy (100 mhz, 32 bit) uni-directional flowconductor pos-phy (8 bit, 100 mhz)
28560-DSH-001-B mindspeed technologies? 2 - 3 advance information cx28560 data sheet host interfaces 2.1.1 pci interface the host interface in the cx28 560 is compliant with the pci local bus specification (revision 2.2). the cx28560 provides a pci interface specific to 3.3 v and 33 mhz operation and supports as master a 32-bit bus with multiplexed address and data lines, and as a slave, a 32-bit pci bus. note: the pci local bus specification (revision 2.2) is an architectural, timing, electrical, and physical interface standa rd that provides a mechanism for a device to interconnect with processor and memory systems over a standard bus. the host interface can act as a pci master and a pci slave, and contains the cx28560?s pci configuration space and internal registers. when the cx28560 needs to access shared memory, it ma sters the pci bus and completes the memory cycles without external intervention. 2.1.1.1 pci initialization generally, when a system initializes a module containing a pci device, the configuration manager reads the configuratio n space of each pci device on a pci bus. hardware signals select a sp ecific pci device based on a bus number, a slot number, and a function number. if a device that is ad dressed (via signal lines) responds to the configuration cycle by claiming the bus, th en that function?s configuration space is read out from the device during the cycl e. since any pci device can be a multi- function device, every supported function?s configuration space needs to be read from the device. based on the information read , the configuration manager will assign system resources to each supported function within the device. sometimes new information needs to be written into the function?s configuration space. this is accomplished with a configuration write cycle. the cx28560 is a single function device that has device-resident memory to store the required configuration information. the cx28560 supports function 0 only. 2.1.1.2 pci bus operations the cx28560 behaves either as a pci master or a pci slave device at any time and switches between these modes as required during device operation. the cx28560 supports only dword write transactions. as a pci slave, the cx28560 responds to the following pci bus operations:  memory read memory write  configuration read  configuration write  memory read multiple (treated li ke memory read in slave mode)  memory read line (treated like memory read in slave mode)  memory write and invalidate (treated like memory write) note: as a pci slave, the cx28560 does not support bursted read or write pci transactions. the cx28560 ignores all other pci cycles. as a pci master, the cx28560 generates the following pci bus operations:  memory read  memory read line  memory read multiple memory write
2-4 mindspeed technologies? 28560-DSH-001-B advance information host interfaces cx28560 data sheet 2.1.1.3 fast back-to-back transactions fast back-to-back transactio ns allow agents to use bus bandwidth more effectively. the cx28560 supports pci fast back-to-back transactions both as a bus target and bus master. the cx28560 can also execute fast ba ck-to-back transactions regardless of the pci configuration settings (for details see bit 11 target_fbtb bit field in chapter 5.0 ). note: the cx28560 will only perform fast back to back between transactions from different sources (either the interrupt co ntroller or the host service unit) and not between transactions from the same source. fast back-to-back transac tions are allowed on pci when contention on trdy*, devsel*, stop*, or perr* is avoided. (for a detailed description of these pins see chapter 1.0 ). the cx28560, as a master supporting fa st back-to-back tran sactions, places the burden of avoiding contention on itself. wh ile acting as a slave, the cx28560 places the burden on all the potential targets. as a master, the cx28560 may remove the idle state between transactions when it can guarantee that no contention occurs. this can be accomplished when the master?s current transaction is to the same target as the previous transaction. while su pporting this type of fast ba ck-to-back transaction, the cx28560 understands the address boundaries of the potential target, so that no contention occurs. the target must be able to detect a new assertion of frame* without the bus going to idle state. operation mode during a fast back-to-back tr ansaction, the master starts the next transaction if gnt* is still asserted. if gnt* is deasserted, the master has lost access to the bus and must relinquish the bus to the next master. the last data phase completes when frame* is deasserted, and irdy* and trdy* (or stop *) are asserted. the current master starts another transaction on the clock foll owing the completion of the last data phase of the previous transaction. during fast back-to-back transaction, only the master and target involved need to distinguish interm ediate transaction boundaries using only frame* and irdy* (there is no bus idle st ate). when the transaction is over, all the agents see an idle state. example of an arbitration for fast ba ck-to-back and non-fast back-to-back transactions appendix g shows an example of an arbitr ation for fast back-t o-back and non-fast back-to-back transact ions. the transactions shown are bursts of 2 or 3 dwords.
28560-DSH-001-B mindspeed technologies? 2 - 5 advance information cx28560 data sheet host interfaces 2.1.1.4 pci configuration space this section describes how the cx28560 im plements the required pci configuration register space. the intent of pci configur ation space definition is to provide an appropriate set of configuration register s that satisfy the needs of current and anticipated system configuration mechanis ms, without specifying those mechanisms or otherwise placing constraints on their use. these registers allow for the following:  full device relocation, including interrupt binding  installation, configuration, and booting without us er intervention  system address map construction by device-independent software the cx28560 responds only to type 0 configuration cycles. type 1 cycles, which pass a configuration request on to another pci bus, are ignored. the cx28560 is a single function pci agent; therefore, it implements configuration space for function 0 only. the pci controller in the cx28560 responds to configuration and memory cycles, but only memory cycles cause bus activity on the ebus. the address phase during a the cx28560 co nfiguration cycle indicates the function number and register number being addresse d, which can be decoded by observing the status of the address lines ad[31:0]. the figure below illustrates the address lines during configuration cycle. the value of the signal lines ad[10:8] select s the function being addressed. since the cx28560 supports function 0 only, it ignores these bits. the value of the signal lines ad[7:2] during the address phase of configur ation cycles selects the register of the configuration space to access. valid valu es are 0 through 15. accessing registers outside this range results in an all 0s va lue being returned on reads, and no action being taken on writes. the value of the signal lines ad[1:0] must be 00b for the cx28560 to respond. if these bits are 0 and the idsel* signal line is asserted, then the cx28560 responds to the configuration cycle. 31 8 7 21 0 don?t care 6 bit register # 2 bit type # note(s): the cx28560 supports function 0 only the cx28560 supports registers 0 through 15 inclusively the cx28560 supports type 0 configuration cycles.
2-6 mindspeed technologies? 28560-DSH-001-B advance information host interfaces cx28560 data sheet the base code register contains the cla ss code, sub class code, and register level programming interface registers. table 2-1 illustrates the pci configuration space. all writable bits in the configuration sp ace are reset to 0 by the hardware reset, prst* asserted. after reset, the cx28560 is disabled and only responds to pci configuration write and pci configuration read cycles. write cycles to reserved bits and registers have no effect. read cycles to reserved bits always result in 0 being read. table 2-1. pci configuration space register number byte offset (hex) 31 24 23 16 15 8 7 0 0 00h device id vendor id 1 04h status command 2 08h base code revision id 3 0ch reserved header type latency timer reserved 4 10h the cx28560 base address register 5?10 reserved 11 2ch subsystem id subsystem vendor id 12?14 reserved 15 3ch max latency min grant i nterrupt pin interrupt line
28560-DSH-001-B mindspeed technologies? 2 - 7 advance information cx28560 data sheet host interfaces 2.2 pci configuration registers 2.2.1 pci master and slave the cx28560 is a single function pci device that provides the necessary configuration space for a pc i bus controller to query and configure the cx28560?s pci interface. pci configuration space consists of a device-independent header region (64 bytes) and a device-dependent header region (192 bytes). the cx28560 provides the device-independent header section only. access to the device-dependent header region results in 0s being read, and no effect on writes. three types of registers ar e available in the cx28560: 1. read-only (ro)?return a fixed bit pattern if the register is used or a 0 if the register is unused or reserved 2. read-resettable (rr)?can be reset to 0 by writing a 1 to the register 3. read/write (rw)?retain the value last written to it. sixteen dword registers make up the cx28560?s pci configuration space. the tables below specify the contents of these registers: 2.2.1.1 register 0, address 00h table 2-2. register 0, address 00h bit field name reset value type 31:16 device id 8563 = 2047 cha nnel hdlc controller ro 15:0 vendor id 14f1h ro
2-8 mindspeed technologies? 28560-DSH-001-B advance information host interfaces cx28560 data sheet 2.2.1.2 register 1, address 04h the status register records status info rmation for pci bus related events. the command register provides co arse control to generate an d respond to pci commands. at reset, the cx28560 sets the bits in th is register to 0, meaning the cx28560 is logically disconnected from the pci bus for all cycle types except configuration read and configuration write cycles. table 2-3. register 1, address 04h (1 of 2) bit field name reset value type description 31 status 0 rr detected parity error. this bit is set by the cx28560 whenever it detects a parity erro r, even if parity error response is disabled. 30 ? 0 rr detected system error. this bit is set by the cx28560 whenever it asserts serr. 29 ? 0 rr received master abort. this bit is set by the cx28560 when ever a cx28560 init iated cycle is terminated with a master abort. 28 ? 0 rr received target abort. this bit is set by the cx28560 when ever a cx28560 init iated cycle is terminated by a target-abort. 27 ? 0 ro unused 26:25 ? 01b ro devsel timing. indicates the cx28560 is a medium spee d pci device. this means the longest time it will take the cx28560 to return devsel when it is a target is 3 clocks. 24 ? 0 rr data parity detected. this bit is set by the cx28560 whenev er the following 3 conditions are met: the cx28560 asserted perr or observed perr the cx28560 was the master for that transactions parity error res ponse bit is set. 23 ? 1b ro fast back-to-back capable. read only. indicates that the cx28560 is capable of accepting fast back-to-back transactions when the transactions are not to the same agent. 22 ? 0 ro unused 21 ? 1b ro not 66 mhz capable. 20:16 ? 0 ro unused 15:10 command 0 ro unused note(s): this value would normally indi cate that the device is ca pable of supporting a 66 mhz clock, but the cx28560 does not.
28560-DSH-001-B mindspeed technologies? 2 - 9 advance information cx28560 data sheet host interfaces 9 ? 0 rw fast back-to-back enable. this bit controls whether or not th e cx28560, while acting as master, can perform fast back-to-back transactions to different devices. the configuration software routine sets this bit if all bus agents in the system are fast back-to- back capable. if 1, the cx28560 can genera te fast back-to-back tr ansactions to different agents. if 0, the cx28560 can genera te fast back-to-back tr ansactions to the same agent. note: this bit would be presumably set by the system configuration routine after ensuring that all targets on the same bus had the fast back-to-back capable bit set. if the target is una ble to provide the fast back-to-back capability, the target does not implemen t this bit and it is automatically returned as zero when st atus register is read. 8 ? 0 rw serr enable. if 1, disables the cx 28560?s serr* driver. if 0, enables the cx28560?s serr* driver and allows reporting of address parity errors. 7 ? 0 ro wait cycle contro l. the cx28560 does not support address stepping. 6 ? 0 rw parity error response. this bit controls the cx28560?s response to parity errors. if 1, the cx28560 takes normal action when a parity error is detected on a cycle as the target. if 0, the cx28560 ignores parity errors. 5 ? 0 ro vga palette snoop. unused. 4 ? 0 ro memory write and invalidate. the only write cycle type the cx 28560 generates is memory write. 3 ? 0 ro special cycles. unused. the cx28560 ignore s all special cycles. 2?0rwbus master. if 1, the cx28560 is permitte d to act as bus master. if 0, the cx28560 is disabled from generating pci acce sses. 1 ? 0 rw memory space. access control. if 1, enables the cx28560 to respond to memory space access cycles. if 0, disables th e cx28560?s response. 0 ? 0 ro i/o space accesses. the cx28560 does not contai n any i/o space registers. table 2-3. register 1, address 04h (2 of 2) bit field name reset value type description
2-10 mindspeed technologies? 28560-DSH-001-B advance information host interfaces cx28560 data sheet 2.2.1.3 register 2, address 08h this location contains the class code and revision id registers. the class code register contains the base code, sub class, and register level programming interface fields. these are used to specif y the generic function of the cx28560. the revision id register denotes the version of the device. 2.2.1.4 register 3, address 0ch table 2-4. register 2, address 08h bit field name reset value type description 31:24 class code 02h ro function: network controller 23:16 sub class code 80h ro type: other 15:8 register level programming interface 0 ro indicates that there is nothi ng special about programming the cx28560. 7:0 revision id 00h ro denotes the revision number of the cx28560. this revision id is divided into two 4 bit fields. upper nibble indicates die id which started from 0 for this device. the lower nibble is used for rev number, rev a = 0, rev b = 1, etc. table 2-5. register 3, address 0ch bit field name reset value type description 31:24 reserved 0 ro unused 23:16 header type 0 ro the cx28560 is a single func tion device with the standard layout of configuration register space. 15:11 latency timer 0 rw the latency timer is an 8-bit value that specifies the maximum number of pci clocks that the cx28560 can keep th e bus after starting the access cycle by asserting its frame*. the latency timer ensure s that the cx28560 has a minimum time slot for it to own the bus, but places an upper limit on how long it owns the bus. 10:8 ? 0 ro ? 7:0 reserved 0 ro unused
28560-DSH-001-B mindspeed technologies? 2 - 11 advance information cx28560 data sheet host interfaces 2.2.1.5 register 4, address 10h 2.2.1.6 register 5?10, address 14h?28h 2.2.1.7 register 11, address 2ch 2.2.1.8 register 12?14, address 30h?38h table 2-6. register 4, address 10h bit field name reset value type description 31:20 cx28560 base address register 0 rw allows for 1 mb-bounded pci bus addres s space to be blocked off as the cx28560 space. the cx28560 will respond as a pci slave with devsel* to all memory cycles whose address bits 31:20 match th e value of bits 31:20 of this register, and those upper address bits are non-zero, and memory space is enabled in the register 1, command bit field. reads to addresses within this space that are not implemented read back 0; writes have no effect. 19:4 ? 0 ro when appended to bits 31:20, th ese bits specify a 1 mb bound memory range. 1 mb is the only amount of address space that a cx28560 can be assigned. 3 ? 0 ro the cx28560 memory spac e is not prefetchable. 2:1 ? 0 ro the cx28560 can be located an ywhere in 32-bit address space. 0 ? 0 ro this base register is a memory space base register , as opposed to i/o mapped. table 2-7. register 5?10, address 14h?28h bit field name reset value type description 31:0 reserved 0 ro unused table 2-8. register 11, address 2ch bit field description reset value type 31:16 subsystem id 8563 = 2047 channel hdlc controller ro 15:0 subsystem vendor id 14f1 ro table 2-9. register 12 ? 14, address 30h ? 38h bit field name reset value type description 31:0 reserved 0 ro unused
2-12 mindspeed technologies? 28560-DSH-001-B advance information host interfaces cx28560 data sheet 2.2.1.9 register 15, address 3ch 2.2.2 pci reset the cx28560 resets all internal functions when it detects the assertion of the prst* signal line. upon reset, the following occurs:  all pci output signals are three-stated immediately and asynchronously with respect to the pci clock input, pclk.  all ebus output signals are three-st ated immediately and asynchronously with respect to the eb us clock output, eclk.  all writable/resettable internal register bits are set to 0.  all pci transfers are terminated immediately.  all serial data transfers are terminated immediately.  all pos-phy transfers are terminated i mmediately. output signals are three- stated immediately and asynchro nously to the pos-phy clocks.  the cx28560 is disabled and responds only to pci configuration cycles.  all data is lost. 2.2.3 pci throughput and latency considerations for reference to pci throughput and latency considerations see appendix h . table 2-10. register 15, address 3ch bit field name reset value type description 31:24 maximum latency 0fh ro specifies how qui ckly the cx28560 needs to gain access to the pci bus. the value is specified in 0.25 s increments and assumes a 33 mhz clock. a value of 0fh means tanfo needs to gain access to the pci bus every 130 pci clocks, expressed as 3.75 s in this register. 23:16 minimum grant 01h ro specifies, in 0.25 s increments, the mi nimum burst period the cx28560 needs. the cx28560 does no t have any special min_gnt requirements. 15:8 interrupt pin 01h ro defines which pci in terrupt pin the cx28560 uses. 01h means the cx28560 uses pin inta*. 7:0 interrupt line 0 rw communicates interrupt line routing. system initialization software writes a value to this register indicating which host interrupt controller input is connect ed to the cx28560?s inta* pin.
28560-DSH-001-B mindspeed technologies? 2 - 13 advance information cx28560 data sheet host interfaces 2.2.4 host interface after a hardware reset, the pci configur ation space within cx28560 needs to be configured by the host as follows:  base address register  fast back-to-back enable/disable  serr* signal driver enable/disable  parity error response enable/disable  latency timer register  interrupt line register  bus mastering enable/disable  memory space access enable/disable
2-14 mindspeed technologies? 28560-DSH-001-B advance information host interfaces cx28560 data sheet 2.3 pos-phy 2.3.1 pos-phy interfaces there are three pos-phy inte rfaces?two for the transfer of data, and one that is used as a feedback bus to the system. in addition to the individual configurations necessary for configuration, the pos- phy registered mode bit in the global configuration register ( section 5.4 ) should be configured. 2.3.1.1 pos-phy registered mode the pos-phy standard sets the timing of the rxenb signal. normal mode (non- registered mode) works exactly according to the standard. non-registered mode delays the timing of the sampling of the rxenb signal by one clock. in order to use the cx28560 with the tsp (mxt4700), the pos-phy should be configured in registered mode. when in registered mode, the cell available (clav) signal is also active. see table 1-9, cx28560 pos-phy interface (receive) . 2.3.1.2 pos-phy data interface in all places where the pos-phy data interfa ce is referred to, the ?transmit side? is the side on which data is transmitted from the host to the cx28560, and the ?receive side? is the side on which the cx 28560 transmits data to the host. the pos-phy data bus implemented in th e cx28560 is compliant to the atm pos- phy level 3 standard (af-phy-0143.000) and supports other industry standards for level 3 packet functionality at 100 mhz clock, and 32 bit wide data bus for the transferal of data fragments. the packet fu nctionality is provided by start of packet and end of packet signals that delimit the fragments. note: the start and end of hdlc packets are indicated in the fragment headers. flow control on the transmit side bus is provided by the ptpa (polled-phy transmit packet available) pin. when there is not en ough space in the buff er to receive further data for transmission, the ptpa pin is set to low. the decision as to whether there is space in the buffers is decided according to two thresholds: an upper threshold, and a lower threshold. the buffers are initially em pty. crossing thresholds has the following affects:  crossing the lower threshold from below has no affect (the ptpa pin remains asserted).  crossing the upper threshold from below de-asserts the ptpa pin (there is no space in the buffer).  crossing the upper threshold from above has no affect (there is still no space in the buffer).  crossing the lower threshold from abov e causes the ptpa pin to be asserted (there is now space in the buffer). the thresholds are set in the transm it pos-phy thresholds register (see chapter 5.0 , transmit pos-phy thresholds register). the upper threshold should be set to the buffer size less the maximum fragment length. the lower threshold should be se t in accordance with the latency of the mechanism deciding whether to send data.
28560-DSH-001-B mindspeed technologies? 2 - 15 advance information cx28560 data sheet host interfaces 2.3.1.3 pos-phy flow conductor interface the pos-phy flow conductor bus implemente d in the cx28560 is compliant to the atm pos-phy level 3 standard (af-phy-0143.000) and supports other industry standards for level 3 packet functionality at 100 mhz clock, and 8 bit wide data bus for the transferal of report packets. this in terface is identical to the receive side data interface provided. the flow conductor pos-phy and the rece ive data pos-phy interfaces are not fully compatible with the pos-phy standa rd. not during data transmission, if frenb/renb is high (not enabled), the other signals change their value on the following clock. during data transmissi on if frenb/renb is high, the cx28560 pos-phy interface stores the old values on the next clock. hence, the system should sample data only if frenb/renb is low on the previous clock. note: the cx28560 will always introduce a minimum of a 2 cycle delay between packets over the pos-phy interface. 2.3.1.4 receive pos-phy initialization no initialization of the pos-phy is necessary. 2.3.1.5 transmit pos-phy initialization to initialize the transmit pos-phy, the fl ow control thresholds should be set (see above) in the data bus. no initialization is necessary for the flow conductor bus.
2-16 mindspeed technologies? 28560-DSH-001-B advance information host interfaces cx28560 data sheet
28560-DSH-001-B mindspeed technologies? 3 - 1 advance information 3.0 expansion bus (ebus) the cx28560 provides an access to a local bus interface called the expansion bus (ebus), which provides a host processor to access any address in the peripheral memory space on the ebus. although eb us use is optional, the most notable applications for the ebus are the connectio ns to peripheral devices, e.g., bt8370/ bt8398 t1/e1 framers, cn8398 (octal ds1/e1 framers), and cx29503/m29513 bam3/bam3+ and cx29610 optiphy that are local to the cx28560?s serial port. similarly to the cn28500, but unlike previous generations of hdlc controllers (cn8478/cn8474/cn8472), the cx28560 provides access to the ebus through an interface similar to a mailbox interface. this interface provides all the ebus read and write accesses to be carried over the pci bus, allowing pci bursts. this mechanism improves the pci use when multiple ebus accesses are necessary for accessing the configuration of peripheral devices. the pc i function 1 is disa bled. therefore, the cx28560?s ebus service requests are capable of accepting or generating burst on the pci bus. however, the ebus interface signals are not capable of performing burst. also, the cx28560 does not interface with eint* signal of the ebus. this signal should be tied directly or via exte rnal logic to the pci interrupt intb*. figures 3-1 and 3-2 illustrate block diagrams of the ebus interface with and without local microprocessor (mpu). figure 3-1. ebus functional block diagram with local mpu ebus interface regenerated and inverted clock address/data clock control bus arbitration address/data local expansion bus bus arbiter mpu intel or motorola t1/e1 framers or t3/e3 101302_005
3-2 mindspeed technologies? 28560-DSH-001-B advance information expansion bus (ebus) cx28560 data sheet figure 3-2. ebus functional block diagram without local mpu ebus interface clock address/data clock control bus arbitration address/data local expansion bus local ram peripheral devices downloadable rom 101302_006
28560-DSH-001-B mindspeed technologies? 3 - 3 advance information cx28560 data sheet expansion bus (ebus) 3.1 ebus?operational mode 3.1.1 initialization after reset and after the pci configuration is completed, the cx28560 provides the host the ability to read and write pe ripheral devices located on the ebus (see table 3-1 ). the host service request mechanis m allows the host to instruct the cx28560 to perform specific ebus operations. the cx28560 can perform bulk service request commands. the service request acknowledge (sack) can be generated either after each service request command or at the en d of each bulk service request, depending on the value of sack ien bit field set in the service request configuration descriptor (see table 3-2 ). the cx28560 processes an srq by reading the table 5-4, service request pointer register which contains the address of the first entry in the host descriptor table. once configured and enabled, the host can configure local devices connected to the ebus by issuing the ebus access service request (ebus_wr or ebus_rd). the command is a three dword memory location that contains the fo llowing dword fields:  access control field  shared memory pointer (buffer address) representing the starting address of the buffer location where the device structure resides  ebus base address offset (the addr ess of the first ebus transaction) table 3-1. ebus service request descriptor dword number bit 31 bit 0 dword 0 opcode[31:27] sackien[ 26] reserved[25:19] fifo_burst[18] ebus byte enable [17:14] length[13:0] dword 1 shared memory pointer[31:2] (2) dword 2 ebus base address offset dword 3 reserved (1) footnote: (1) all reserved bits must be written with 0s for forward compatibility. (2) the two lsbs must be equal to zero for dword alignment.
3-4 mindspeed technologies? 28560-DSH-001-B advance information expansion bus (ebus) cx28560 data sheet table 3-2. ebus service request field descriptions dword number descriptor field size (bits) value description dword 0 opcode 5 6 ebus write command (ebus_wr) 7 ebus read command (ebus_rd) sackien 1 ? enable (1) or disable (0) acknowledge via interrupt in the end of the command execution reserved 7 0 reserved bits s hould be written with 0s. fifo_burst 1 0 do increment ebus address (address on the target device) by one after each ebus access. this is used to access a continuous segment or block of memory on the target devi ce that is connected to the ebus. 1 do not increment ebus address for this access. on some devices, memory accesses are carried out the writing/reading of one memory location. by setting fifo_burst to one, cx28500 does not increment the ebus address after an access. hence, the address stays the same for the next ebus access. ebus byte enable (ebe) 4 ? the value driven over ebe[3:0]*. each bit controls a corresponding byte access on the ebus. for exam ple, an ebe[3:0] value of 0001 means that host data passes to the device attached to the ebus on byte 0, the least signifi cant byte, of the ebus while the other three bytes are inaccessible. length 14 ? number of ebus transactions. dword 1 shared memory pointer 32 ? the shared memory pointer (buffer address) is a dword?aligned address of the first buffer to or from which data needs to be transferred from or to the ebus. the two lsb?s must be equal to zero for dword alignment. dword 2 ebus base address offset 32 ? the ebus base addr ess offset is the address for the first ebus transaction.
28560-DSH-001-B mindspeed technologies? 3 - 5 advance information cx28560 data sheet expansion bus (ebus) the shared memory pointer (buffer address) is a dword?aligned address of the first buffer to or from which data needs to be transferred from or to the ebus. the ebus base address offset is the address for the first ebus transaction. in the access control field, the length bit field contains the information of the number of bytes transferred over the pci. the maximum pci bu rst read or write of ebus transactions is 32 dwords. when an ebus_rd is issued, the cx28560 executes a pci-bursted write of ebus transactions and will store the data (ead[31:0]) in an internal buffer. when the ebus transaction ends, the cx28 560 bursts the data over the pci to the location specified by shared memory po inter (buffer addre ss). the ebe[3:0]* drives the programmed byte enabled (be) value set in the access control field dword. if ebe[3:0]* is different from 0000, the host must determine which bytes are valid. if an ebus write command is enabled, the cx28560 transfers?via a pci burst read?the data from the host memory into an internal buffer. the data is transferred over the ebus in a series of write transactions. the ebe[3:0]* drives the programmed value byte enabled (be) value se t in the access control field dword. if ebe[3:0]* is different from 0000, the host must insert the valid bytes into the appropriate location. 3.1.2 clock the eclk, expansion bus clock, is an inverted version of the pci clock. the signal is output on the eclk signal line. whether or not a device on the ebus requires a synchronous interface, the eclk signal is available all the time the pci clock is available (pclk). the ebus clock output can be disabled by appropriately setting the ecken bit field in ebus configuration register. if eclk is disabled, the eclk output is three-stated. after pci reset, the eclk ou tput pin is three-stated and the ecken field in ebus configuration register is cleared. 3.1.3 interrupt similar to the cn28500, but unlike previous hdlc controllers (cn8478/cn8474/ cn8472), the cx28560 is not connected to the eint* pin of the ebus. the ebus interrupt line should be connected to pci interrupt intb* directly, if it is needed. 3.1.4 address duration the cx28560 can extend the duration that the address bits are valid for any given ebus address phase. this is accomplished by specifying a value from 0?3 in the alapse bit field in ebus configuration register. the value specifies the additional eclk periods the address bits remain asserted. that is, a value of 0 specifies the address remains asserted for one eclk period, and a value of 3 specifies the address remains asserted for four eclk periods. disabling the eclk signal output does not affect the delay mechanism. both pre- and post-address cycles are always present during the address phase of an ebus cycle. the pre-address cycle is one eclk period long and provides the cx28560 time to transition between the ad dress phase and the following data phase. the pre- and post-cycles are not in cluded in the address duration.
3-6 mindspeed technologies? 28560-DSH-001-B advance information expansion bus (ebus) cx28560 data sheet 3.1.5 data duration the cx28560 can extend the duration that the data bits are valid for any given ebus data phase. this is accomp lished by specifying a value from 0?7 in the elapse bit field in ebus configuration register. the value specifies the additional eclk periods the data bits remain asserted. that is, a value of 0 specifies the data remains asserted for one eclk period, and a value of 7 specifies the data remains asserted for eight eclk periods. disabling the eclk signal output does not affect the delay mechanism. a pre- and post-data cycle is always present during the data phase of an ebus cycle. the pre-data cycle is one eclk period lo ng and provides the cx28560 sufficient setup and hold time for the data signals. th e post-data cycle is one eclk period long and provides cx28560 sufficient time to transition between the data phase and the following bus cycle termination. the pre- and post-cycles are not included in the data duration. 3.1.6 bus access interval the cx28560 can be configured to wait a specified amount of time after it releases the ebus and before it requests the ebus . this is accomplished by specifying a value from 0?7 in the blapse bit field in ebus configuration register. the value specifies the additional eclk periods the cx28560 waits immediately after releasing the bus. that is, a value of 0 specifies a wait of one eclk period, and a value of 5 specifies six eclk periods. disabling the ec lk signal output does not affect this wait mechanism. the bus grant signal (hld a/bg*) is deasserted by the bus arbiter only after the bus request si gnal (hold/br*) is deasserted by the cx28560. as the amount of time between bus request deassertion and bus grant deassertion can vary from system to system, it is possible for a mi sinterpretation of the old bus grant signal as an approval to access the ebus. the cx28560 provides the flexibility?through the bus access interval feature?to wait a specific number of eclk periods between subsequent bus requests. refer to ebus timing diagrams?figure 9-8, ebus write/read cycle, intel-style (intel) and figure 9-9, ebus write/read cycle, motorola-style (motorola). 3.1.7 pci to ebus interaction the cx28560 provides an identical ebus interface to the cx28500 that is a significant improvement compared to previous hdlc devices (cn8478/cn8474/ cn8472). pci utilization is dramatically improved by enabling the ebus accesses, reads and writes, to be burst over the pci bus?when ebus is extensively used to access ebus peripheral during normal operation.
28560-DSH-001-B mindspeed technologies? 3 - 7 advance information cx28560 data sheet expansion bus (ebus) 3.1.8 microprocessor interface the mpusel bit field in ebus configuration register specifies the type of microprocessor interface to use for the ebus. if intel-style protocol is selected, the following signals are effective:  ale* ? address latch enable, asserted low by the cx28560 to indicate that the address lines contain a valid address. this signal remains asserted for the duration of the access cycle. rd* ? read, strobed low by the cx28560 to enable data reads out of the device and is held high during writes. wr* ? write, strobed low by the cx28560 to enable data writes into the device and is held high during reads. hold ? hold request, asserted high by the cx28560 when it requests the ebus from a bus arbiter. hlda ? hold acknowledge, asserted high by bus arbiter in response to hold signal assertion. remains asserted until after the hold signal is deasserted. if the ebus is connected and there are no bus arbiters on the ebus, this signal must be asserted high at all times. if motorola-style protocol, the following signals are effective: as* ? address strobe, driven low by the cx 28560 to indicate that the address lines contain a valid address. this sign al remains asserted for the duration of the access cycle. ds* ? data strobe, strobed low by the cx28560 to enable data reads or data writes for the addressed device. r/wr* ? read/write, held high throughout read operation and held low throughout write operation by the cx 28560. this signal determines the meaning (read or write) of ds*. br* ? bus request, asserted low by the cx28560 when it requests the ebus from a bus arbiter. bg* ? hold acknowledge, asserted low by bus arbiter in response to br* signal assertion. remains asserted until after the br* signal is deasserted. if the ebus is connected and there are no bus arbiters on the ebus, this signal must be asserted low at all times. bgack* ? bus grant acknowledge, asserted low by the cx28560 when it detects bgack* currently deasserted. as this signal is asserted, the cx28560 begins the ebus access cycle. after th e cycle is finished, this signal is deasserted indicating to the bus arbite r that the cx28560 has released the ebus.
3-8 mindspeed technologies? 28560-DSH-001-B advance information expansion bus (ebus) cx28560 data sheet 3.1.9 arbitration the hold and hlda (intel) or br* and bg* (motorola) signal lines are used by the cx28560 to arbitrate for the ebus. for intel-style interfaces, the arbitration pr otocol is as follows (see figure 9-8, ebus write/read cycle, intel-style ). 1. the cx28560 three-states ead[31:0], ebe*[3:0]. wr*, rd*, and ale*. 2. the cx28560 requires ebus access and asserts hold. 3. the cx28560 checks for hlda assertion by bus arbiter. 4. if hlda is found to be deasserted, the cx28560 waits for the hlda signal to become asserted before continuing the ebus operation. 5. if hlda is found to be asserted, th e cx28560 continues with the ebus access as it has control of the ebus. 6. the cx28560 drives ead[31:0], ebe*[3:0], wr*, rd*, and ale*. 7. the cx28560 completes ebus access and deasserts hold. 8. bus arbiter deasserts hl da shortly thereafter. 9. the cx28560 three-states ead[31:0], ebe*[3:0]. wr*, rd*, and ale*. for motorola-style interfaces, the arbitration protocol is as follows (refer to figure 9- 9, ebus write/read cycle, motorola-style ). 1. the cx28560 three-states ead[31:0], ebe*[3:0]. r/wr*, ds*, and as*. 2. the cx28560 requires ebus access and asserts br*. 3. the cx28560 checks for bg* assertion by bus arbiter. 4. if bg* is found to be deasserted, the cx28560 waits for the bg* signal to become asserted before continuing the ebus operation. 5. if bg* is found to be asserted, the cx28560 continues with the ebus access as it has control of the ebus. 6. if bgack* is not asserted, the cx28560 assumes control of the ebus by asserting bgack*. 7. the cx28560 drives ead[31:0], ebe*[3:0], r/wr*, ds*, as*. 8. shortly after the ebus cycle is st arted, the cx28560 deasserts br*. 9. bus arbiter deasserts bg* shortly thereafter. 10. the cx28560 completes ebus cycle. 11. the cx28560 deasserts bgack*. 12. the cx28560 three-states ead[31:0], ebe*[3:0]. r/wr*, ds*, and as*.
28560-DSH-001-B mindspeed technologies? 3 - 9 advance information cx28560 data sheet expansion bus (ebus) 3.1.10 connection using the ebus address lines, ead[17:0], and the byte enable lines, ebe[3:0]*, the ebus can be connected in either a multip lexed or non-multiplexed address and data mode. figures 3-3 and 3-4 illustrate two examples of non-multiplexed address and data modes. figures 3-5 and 3-6 illustrate four and eight se parate byte-wide framer devices connected to the ebus with e ach byte enable line used as the chip select for separate devices, which allows a full dword data transfer over the ebus. the framers configuration in shared memory is that only the least significant byte (lsb) contains the information of one frame configuration; the others are unused. figure 3-3. ebus connection, non-multiplexed address/data, 8 framers, no local mpu bt8370 data cs* bt8370 cs* bt8370 cs* bt8370 cs* ead[31:24] ead[23:16] ead[15:8] ead[7:0] ead[8:0] cx28560 ead[31:0] device 0,4 device 3,7 ebe[3:0]* as*, r/wr*, ds*, eclk control lines ebe[0]* ebe[1]* ebe[2]* ebe[3]* ead9 chip select logic dev 0,4 device 2,6 device 1,5 addr data addr data addr data addr 101302_007 note(s): 1. ebex[3:0]* selects device x in each framer block. 2. ead[31:0], as* are supplied to each framer block. 3. ebex*, as* are supplied to each chip select block.
3-10 mindspeed technologies? 28560-DSH-001-B advance information expansion bus (ebus) cx28560 data sheet in the multiplexed address and data mode , four byte-wide peripheral devices are connected to the ebus. in this mode, 8 bits of the 32-bit ebus transfer data to and from each device individually. note: the multiplexed address and data mode ex ample does not allow for 4-byte data transfers. figure 3-4. ebus connection, non-multiplexed address/data, 16 framers, no local mpu bt8370 cs* bt8370 cs* bt8370 cs* ead[31:24] ead[23:16] ead[15:8] ead[8:0] framer bank 0 framer bank 1 framer bank 2 framer bank 3 dev 0, bank 0 dev 0, bank 1 dev 0, bank 2 ead[10, 9] ebe[3:0]* ead[31:0] dev 0 8 98 98989 chip select logic cx28560 control lines control bt8370 data addr data addr data addr data addr cs* dev 0, bank 3 dev 3 dev 2 dev 1 ead[7:0] 101302_008 note(s): 1. ebex[3:0]* selects device x in each framer block. 2. ead[31:0], as* are supplied to each framer block. 3. ebex*, as* are supplied to each chip select block.
28560-DSH-001-B mindspeed technologies? 3 - 11 advance information cx28560 data sheet expansion bus (ebus) figure 3-5 illustrates the ebus connection, mu ltiplexed address/data, 8 framers, no local mpu. 3.1.10.1 multiplexing address figure 3-6 illustrates the ebus conn ections of four 8-bit peripheral devices. the four devices are multiplexing the address in sh ared memory. the framer?s configuration software must read the whole block of framers configuration before it starts demultiplexing data per device. figure 3-5. ebus connection, multiplexed address/data, 8 framers, no local mpu as*, r/wr*, ds*, eclk control lines cs0*,cs4* cs1*,cs5* cx28560 cs2*,cs6* cs3*,cs7* ebe[3:0]* bt8370 data addr data addr data addr data addr cs* bt8370 cs* bt8370 cs* bt8370 cs* ead[8:0] chip select ead[10:9] 101302_009 figure 3-6. ebus connection, multiplexed address/data, 4 framers, no local mpu ebus cx28560 ead[31:0] addr latch bt8370 bt8370 bt8370 bt8370 be2 be1 be0 ead[0:7] ad[0:x] ead[8:15] ead[16:24] ead[25:31] a0?a9 a0?a9 a0?a9 a0?a9 101302_010
3-12 mindspeed technologies? 28560-DSH-001-B advance information expansion bus (ebus) cx28560 data sheet
28560-DSH-001-B mindspeed technologies? 4 - 1 advance information 4.1 functional description the serial interface consists of the following:  serial interface unit (siu), tsiu, an d rsiu for the receive and transmit directions  serial line processing (slp), tslp, and rslp for the receive and transmit directions  buffer controller (buffc), rbuffc, and tbuffc for the receive and transmit directions  interrupt controller (ic) a separate set of siu, slp, and buffc blocks services receive and transmit channels independently. a single interrupt controller is shared by the receive and transmit buffc, slp, and siu blocks. figure 4-1 illustrates the different signal connection between siu and the host interface while it is configur ed to operate in conventio nal or with ds0 extraction mode. 4.0 cx28560 serial interface
4-2 mindspeed technologies? 28560-DSH-001-B advance information cx28560 serial interface cx28560 data sheet figure 4-1. serial interface functional block diagram 101302_011 rx data rx event/ host commands tx data interrupts rxbuffc interrupt controller txbuffc rxslp txslp rx event / error tx event / error rx event / error tx event / error mask enabled, cofa first ts, chan num, oof data mask enabled, cofa first ts, chan num, cts data buffer info error tx event/ error rxpos fcpos pci txpos txsiu rxsiu
28560-DSH-001-B mindspeed technologies? 4 - 3 advance information cx28560 data sheet cx28560 serial interface 4.2 serial interface unit (siu) the siu is the module that logically connects the 32 serial ports (line interface unit) with serial line processing by performing the serial-to-parallel conversion for the receive side, and parallel-to-serial for the transmit side. the siu contains two main blocks, rsiu for the receive pa th and tsiu for the transmit path. the rsiu main function is multiplexing 32 se rial ports into one logical port for the receive serial line processing block. the tsiu main function is demultiplexing one logical port from the transmit serial line processing block to 32 serial ports. the siu main functions:  multiplexing/demultiplexing 32 serial ports to 1 port for the receive path, and 1 port to 32 serial ports for the transmit path.  performs frame integrity check while operating in channelized mode. siu verifies the length of incoming/outgoing frames according to the configured number of time slots. in case of error, a change of frame alignment (cofa) is reported (see section 4.6.2 and section 4.7.3 ).  translates the time slot to logical channel number using the configured receive and transmit time slot map.  in tsbus mode, in the receive direction, discards stuffed time slots, and in the transmit direction, st uffs time slots as required.  generates the following interrupts: - rxoof, when roof signal is asserted - rxfrec, when roof signal is deasserted - rxcofa, when rsync signal is asserted at an unexpected time - rxcrec, when cofa condit ion ends on a receive port - txcofa, when tsync signal is asserted at an unexpected time - txcrec, when cofa condition ends on a transmit port.
4-4 mindspeed technologies? 28560-DSH-001-B advance information cx28560 serial interface cx28560 data sheet 4.3 serial line processor (slp) the serial line processors (rslp and tslp ) service the bytes in the receive and transmit path. the slp coordinates all by te-level transactions between siu and buffc. the slp also interacts with the interrupt controller (ic) to notify the host of events and errors during the serial line processing. the rslp main features are as follows:  hdlc mode handling - message delineation?search for opening and closing flag (7eh) - abort detection (7fh) - check max/min message length - verify byte alignment -check fcs - detect change of pad-fill - zero deletion  transparent mode - start to receive data from the first time slot assigned to the logical channel  handle channel acti vation/deactivation handle oof/cofa  invert incoming data  handle subchanneling interrupts ? buff?channel-specific buffer error (underrun) ? chic?change to idle code?denotes a change of the inter-message pad-fill from an abort sequence (all 1s) to flags (7eh) ? chabt?change to abort code?denotes a change of the inter- message pad-fill from flags (7eh ) to an abort sequence (all 1s). the tslp main features are as follows:  hdlc mode handling - generate opening/closing /shared flag (7eh) - aborting of packets (generation of abort signal?all 1s) - zero insertion after five consecutive 1s - generate fcs depending upon the protocol -handle cts - generate pad fill between frames  transparent mode - start to transmit data from the first time slot assigned to the logical channel - generate pad fill between messages  handle channel acti vation/deactivation handle cofa  invert outgoing data  handle subchanneling interrupts - buff?channel specific buffer error (underrun) - eom?end of message
28560-DSH-001-B mindspeed technologies? 4 - 5 advance information cx28560 data sheet cx28560 serial interface 4.4 buffer controller the buffer controllers (rxbuffc and txbuffc) manage all memory operations between the slps and the host interface. the buffc receives requests from the slps either to fill or to flush internal fifo buffers, provides/ receives data for the slps, controls the flexiframe timi ng scheduler, and transfers data to/from the pos-phy data interface (t hrough the host interface). in addition, the txbuffc communicates with the system across the pos-phy flowconductor interface by sending repo rt packets containing information regarding the amount of spac e freed in channels? buffers. the buffc main features are as follows:  handles up to 2047 logical channels  static internal buffer allocation  user has full control of internal buffer characteristics: - standard buffer length can be increased to support longer fragments - user-programmable thresholds in the transmit direction - fifo flushing capability (after soft chip reset, channel activation, and channel deactivation service request)  message/fragment handling - addition/interpretation of message and fragment headers  automatic tx abort command generation from terr pin  flexiframe characteristics: - time division scheduling scheme - maximum 21,504 k slots per frame - enables dynamic channels reconfiguration - configurable gap between services - in the transmit direction, controls flowconductor requests  receive performance monitoring counters: -octets -packets - packets with alignment errors - packets with too short errors - packets with too long errors - packets with fcs errors - packets terminating in an abort  transmit performance monitoring counters: -octets -packets - packets transmitted terminating in an abort signal  receive interrupts - rx eom?end of message without an error - rx eom?end of message with er ror (overflow, oof, cofa, fcs, align, abt, lng) - sht?too short. also used as a general errored message interrupt when data has not yet been passed on for a message. (e.g., a 9-bit message)  transmit interrupts - txbovflw?buffc channel buffer overflow - txposerr?an error occurred on the pos-phy flowconductor pos-phy buffer overflow, data pos-phy parity error, data pos- phy txerr pin asserted, or da ta pos-phy internal buffer overflow.
4-6 mindspeed technologies? 28560-DSH-001-B advance information cx28560 serial interface cx28560 data sheet  general interrupts (generated for both receive and transmit) - end of channel command (activation, deactivation) execution interrupt - nfframei? change to the new flexiframe is complete
28560-DSH-001-B mindspeed technologies? 4 - 7 advance information cx28560 data sheet cx28560 serial interface 4.5 interrupt controller the interrupt controller takes receive an d transmit events/errors from rxsiu, rxslp, rxbuffc, and txsiu, txslp, and txbuffc respectively. the interrupt controller coordinates the transfer of internally queued descriptors to an interrupt queue in shared memory, and coordinates notification of pending interrupts to the host. 4.6 serial port interface definition in conventional mode a receive serial port interface (rsiu) connects to four input signals: rclk, rdat, rsync, and roof. a transmit serial port interface (tsiu) connects to three input signals and one output si gnal: tclk, tsync, tcts, and tdat, respectively. the siu receives and transm its data bytes to the transmit serial line processor (tslp) and the receive serial line processor (rslp). the receive and transmit data and synchroni zation signals are sy nchronous to the receive and transmit line clocks, respectively. the cx28560 can be configured to sample in and latch out data signals, and sample in status and synchronization signals on either the rising or falling edges of the respective line clock, namely rclk and tclk. this configuration is accomplished by setting the roof_edge, rsync_edge, rdat_edge, tsync_edge, and tdat_edge bit fields. the default, after reset, is to sample in and latch out data synchronizatio n and status on the falling edges of the respective line clock. the port mode is configured by programming the rport_type and tport_type bit fiel ds. when configured to operate in co nventional mode, the receive and transmit directions are not rela ted to each other, so each direction can be programmed independently of the other.
4-8 mindspeed technologies? 28560-DSH-001-B advance information cx28560 serial interface cx28560 data sheet 4.6.1 frame synchronization flywheel to maintain a time-base, in conventi onal mode, the cx28560 uses the tsync and rsync signals. these signals keep track of the active bit in the current time slot. the mechanism is referred to as the frame synchronization flywheel. the flywheel counts the number of bits per frame and automatically rolls over the bit count according to the programmed mode. the tsync or rsync input marks the first bit in the frame. the mode spec ified in the rport_type bit field and tport_type bit and the start and end addr ess of time slot pointer determine the number of bits in the frame. a flywheel exists for both the transmit and the receive functions for every port. the flywheel is synchronized when the cx28560 detects tsync = 1 or rsync = 1, for transmit or receive functions, respectively. once synchronized, the flywheel maintains synchronization without further assertion of the synchronization signal. a time slot counter within each port is reset at the beginnin g of each frame and tracks the current time slot being serviced. note: in unchannelized mode, the cx28560 ignores the synchronizing signals and the frame synchronization fl ywheel mechanism is ignored. 4.6.2 change of frame alignment (cofa) a change of frame alignment (cofa) condition is defined as a frame synchronization event detect ed when it was not expect ed, and also includes the detection of the first occurrence of frame synchronization in the receive direction. in unchannelized mode, there are no co fa conditions because the tsync and rsync signals are ignored in this mode. when the serial interface detects a cofa condition, an internal cofa signal is asserted until the cofa condition is decl ared off. a cofa condition is declared off when there was a complete frame without an unexpected sync pulse. thus, an internal cofa signal is asserted fo r at least two frame periods. during the frame period that the internal cofa is asserted, the cx28560?s serial line processor (slp) terminates all messages found to be active during the cofa condition relevant to that port. assertion of cofa condition generate s a cofa interrupt encoded in the interrupt status descriptor (isd) toward the host if this in terrupt is unmasked (see rcofa_en or/and tcofa_en bit field s). if a synchronization signal (sync) is received (low to high transition on tsync or rsync) while the internal cofa is asserted, an interrup t descriptor with the cofa interrupt encoding is generated immediately if th is interrupt is not masked. when the internal cofa is deasserted, the cx28560 generates an interrupt descriptor with crec event encoding if the interrupt is unmasked?this includes the cofa caused by the first sync received in the receive direction. on assertion of the internal cofa, in the receive direction an end of message status is prepared with the error encodi ng set to cofa and passed to the system. the receive serial bit stream processing resumes when the cofa condition is declared off. if channels are config ured in hdlc mode, channels resume immediately after the cofa condition is declared off. when configured to transparent mode, channels start operating in the first time slot assigned to the logical channel. thus, after an rxcofa, no channel recovery action is required because the channel recovers automatically.
28560-DSH-001-B mindspeed technologies? 4 - 9 advance information cx28560 data sheet cx28560 serial interface in the transmit direction, the tslp aborts the messages, immediately deactivates the relevant channels, and reports the de activation to the tbuffc. the tbuffc flushes the channels buffer and waits fo r an activation command. as a recovery channel action, the host mu st re-activate the channel upon termination of the cofa condition. cofa detection is not ap plicable in unchan nelized mode. when cofa condition occurs, the transmit output is three-stated. if operating in t1 mode, the f-bit may not be three- stated after a cofa condition. 4.6.3 out of frame (oof )/frame recovery (frec) the receiver out-of-frame (roof) signal is asserted by the serial interface sourcing the channelized data to the cx28560. this signal indicates that the interface device has lost frame synchronization. in the case of multiplexed e1 lines (2xe1, 4xe1), any given port roof signal may be asserted and deasserted as the time slots are received from an out-of- frame (oof) e1 followed by an in-frame e1 . roof assertion is detected by the receiver serial interface (rsiu). if roof is asserted (transitions from low to high) and oofien bit field in the rsiu po rt configuration descriptor is set, an oof interrupt is generated toward the host. for each receive hdlc message that enco untered an oof condition, an end of message status is prepared with the error encoding set to oof and passed to the system. for transpar ent mode channels, the oof cau ses the data that is being transferred to the host to be replaced by an all 1s sequence. no special actions are taken in this case, and the host must rely on the oof interrupt to learn about the oof. one to three time slots after roof is asserted, the cx28560 generates an interrupt descriptor with the oof er ror encoded in the interrupt status descriptor. while roof is asserted, if oofabt bit field in the rsiu port configuration descriptor is set, the receive process is disabled. thus, the cx28560 terminates any active messages fo r all active channels operating over the port; otherwise, the receive process is enabled. notice that the oof signal is examined on a per-time slot ba sis. therefore, oof assertion affects only those logical channels mapped to time slots where oof is asserted. the remaining time slots on the same serial port are not affected by the oof assertion on a specific time slot. as roof is deasserted, the cx28560 immediately restarts normal processing on all active channels. one to three time slots after deassertion of roof is detected, the cx28560 generates an interrupt descriptor with the frec (frame recovery) interrupt encoding if the interrupt is not masked (oofien = 1, rsiu port configuration descriptor). 4.6.4 general serial port interrupt roof signal can be used as a general se rial port interrupt (sport). if oofabt is zero, oofien is set and roof signal d easserts, sport interrupt is generated, and the data stream processing is not affected. when roof transitions from low to high, the sport interrupt is cleared.
4-10 mindspeed technologies? 28560-DSH-001-B advance information cx28560 serial interface cx28560 data sheet 4.6.5 channel clear to send (cts) the cx28560?s transmit path can be configured to obey a channel clear to send (cts) external signal on a per-port basis by enabling the cts_enb bit in the tsiu port configuration register. cts is sampled on the specified active edge of tclk depending on cts_edge. if cts is deasserted (low), the channel a ssigned to the time sl ot sends continuous idle characters after the current message has been completely transmitted. if cts is asserted (high), message transmission contin ues. when config ured to operate in cts mode, the channels of this specific port will not start a new message transmission if the cts is a logical 0. the channel response time to react to changes in the channel cts signal is 32 bits. 4.6.6 frame alignment to maintain a time-base, in conventi onal mode, the cx28560 uses the tsync and rsync signals. these signals keep track of the active bit in the current time slot. the mechanism is referred to as the frame synchronization flywheel. the flywheel counts the number of bits per frame and automatically rolls over the bit count according to the programmed mode. the tsync or rsync input marks the first bit in the frame. the mode spec ified in the rport_type bit field and tport_type bit field in, and the start and end address of time slot pointer determine the number of bits in the frame. a flywheel exists for both the transmit and the receive functions for every port. the flywheel is synchronized when the cx28560 detects tsync = 1 or rsync = 1, for transmit or receive functions, respectively. once synchronized, the flywheel maintains synchronization without further assertion of the synchronization signal. the serial data stream that the cx28560 can manage cons ists of either packetized data or unpacketized data. the cx2856 0 supports two types of data-stream modes: hdlc and transparent. in transparent mode, message processing for every channel begins in the first time slot marked as the first time slot in the channel?s frame structure. a user must configure the first time slot in the rsiu time slot configuration descriptor and tsiu time slot configuration descriptor. for a channel configured in hdlc mode ?either transmit or receive directions? the channel waits for a synchronizat ion signal from the internal frame synchronization flywheel before starting processing a new message after channel activation. a frame synchronization signal must be provided once, after that, the cx28560 keeps track of subsequent frame bit loca tion with its flywheel mechanism. the frame alignment is not relevant when th e port is configured in unchannelized mode, although in unchannelized mode eac h time slot is treated as the first time slot. by configuring more than one time slot in unchannelized mode, (i.e., using tts_endad /rts_endad and tts_startad/rts_startad mechanism to define one frame).
28560-DSH-001-B mindspeed technologies? 4 - 11 advance information cx28560 data sheet cx28560 serial interface 4.7 serial port interface definition tsbus mode a port operation mode is configured by programming the tport_type and rport_type bit fields in rsiu and tsiu port configuration registers. when configured to operate in tsbus mode, the receive and transmit directions are tied to each other. the same tport_type/rport_type must have the same number of time slots configured fo r each tsbus port, and tstb must be programmed the same for both directions, receive and transmit. 4.7.1 tsbus frame synchronization flywheel the cx28560 uses the tstb signal to ma intain a time-base that keeps track of the active bit in the current time slot. th e mechanism is referred to as the frame synchronization flywheel. the flywheel counts the number of bits per frame and automatically rolls over the bit count according to the programmed mode. the tstb input marks the first bit in the fra me. a flywheel exists for both transmit and the receive directions for each port. the tstb assertion works the first bit of time slot in the tsbus frame. the flyw heel is synchronized when the cx28560 detects tstb = 1. once synchronized, th e flywheel maintains synchronization without further assertion of the synchronization signal. a time slot counter within each port is reset at the beginning of ea ch frame and tracks the current time slot being serviced. 4.7.2 tsbus group sync hronization flywheel in twelve of the cx28560?s serial ports, group extraction is supported. this mode will normally be used to extract ds0 signals from a higher level of signal multiplexing, though is fully configurable for any system. the group extraction synchronization uses two extra signals, tgsync and rgsync, that are found only in the first twelve ports in order to maintain a time-base that keeps track of the active bit in the current time slot within a group. the mechanism is referred to as the group synchronization flywheel. the mechanism is used when the present time slot as pointed to in the frame synchronization flywheel is configured to be a group time slot. in this case, the group number is retrieved and the group time slot map is referred to. the flywheel is synchronized when the cx28560 generates tgsync = 1 or detects rgsync = 1. once synchronized, the flywheel maintains synchronization without further assertion of the group synchronization signal. the flywheel counts the number of time slots per group and automatically rolls over the count. the tgsync and the rgsync input marks the first time slot of a group. flywheels exist for both transmit and receive directions for each group.
4-12 mindspeed technologies? 28560-DSH-001-B advance information cx28560 serial interface cx28560 data sheet 4.7.3 tsbus change of frame alignment (cofa) there is no cofa detection in tsbus mo de. if a sync signal is detected, the flywheel mechanism returns the current time slot pointer to the start of the port's allocation. it is therefore recommended to set the cofaien (see table 5- 39, rsiu port configuration register and table 5-53, tsiu port configuration register ) to 0 for tsbus ports to avoid rece iving a cofa interrupt on the first sync signal. 4.7.4 tsbus out of frame (o of)/frame recovery (frec) there is no out of frame (oof) condit ion while operating in tsbus mode. the roof signal is used as a tstb input pin. for reference see figure d- 1, cx28560 time slot interface pins . 4.7.5 tsbus frame alignment the serial data stream that the cx28560 can manage cons ists of either packetized or unpacketized data. the cx28560 supports two types of data-stream modes: hdlc and transparent. in transparent mode, message processing for every channel begins in the time slot marked as the first time slot in the chan nel?s structure. regardless of the channel protocol, the user must configure the first time slot for both receive and transmit directions. for a channel configured for hdlc mode, either transmit or receive direction, the channel waits for a synchronizat ion signal from the internal frame synchronization flywheel before starting processing new messages after channel activation. a frame synchronization signal (tstb) mu st be provided one time; after that, the cx28560 keeps track of subsequent frame bit location within the flywheel mechanism. 4.7.6 tsbus channel clear to send while operating in tsbus mode, there is no cts signal because the related input pin is defined to be tstb (for reference see figure d-1, cx28560 time slot interface pins and table 1-6, serial interface (general) .
28560-DSH-001-B mindspeed technologies? 4 - 13 advance information cx28560 data sheet cx28560 serial interface 4.7.7 tsbus interface the tsbus is a time slot interface. the digital communication data paths and overhead channels consist of payload data and overhead data derived from either sonet or sdh data streams, and payload and overhead data derived from either electrical ds3 or e3 data streams. one of the overhead channels may consist of hdsl messages generated and received by the command status processor (csp). the messages are provided by the local processor that is connected to access and configure local device registers. the tsbus interface is capable of full-duplex (bi-directional) transmission of data between one device and the cx28560 device. the interface consists of two, 1-bit wide serial interfaces: a bi- directional payload tsbus and bi-directional overhead tsbus. a tsbus frame structure is defined as an integer multiplication of bytes. a tsbus port can be either ds0 extraction (group extraction and synchronization is performed) or non-ds0 extraction (group extraction and synchronization is not performed). when a port is defined as tsbus non-ds0 extraction, its interface is defined by seven signals. when a port is defined as tsbus ds0 extraction, its interface is defined by nine signals?the standard se ven signals from the non-ds0 extraction mode, and an extra two group synchronization signals. in the tsbus mode, the rx and tx are synchronous (i.e., the first bit of tx and rx frame is sampled on the falling or rising edge of rclk/tclk on tdat/ rdat). tstb defines the frame synchroniz ation, which marks the first bit of the rx/tx frame. tstuff acts as a flow contro l signal that indicates ?stuff ? (update) to be sent on the following time slot mapped to the logical channel. tstuff is sampled in the first two bits of the channel?s time slot. in the tsbus transmit direction, the cx 28560 requires the stuff status for each time slot to be presented at its tstuff input exactly eight ti me slots in advance of the actual time slot for which the stuff status is applied. the amount of the tstuff advance is fixed at eight time slot s even though the number of time slots within a frame might vary. in ds0 extraction mode, an extra signal (tgsync) performs group synchronization. for the receive direction, cx28560 requires the stuff status for each time slot to be presented at its rstuff input on the current time slot for which the stuff is applied. in ds0 extraction mode, an extra signal (rgsync) performs group synchronization.
4-14 mindspeed technologies? 28560-DSH-001-B advance information cx28560 serial interface cx28560 data sheet 4.7.7.1 payload tsbus examples of the payload tsbus operates at a data rate of 51.84 mbps. it carries the data path signals derived from eith er sonet, sdh, electrical ds3 or the electrical e3 signals. the data on the payload tsbus is framed and consists of 84 time slots. payload data paths are as follows:  sonet/sdh payload  electrical ds3 to ds1?28 x ds1 (672 ti me slots; f-bits not mapped with ds1 signals)  electrical e3 to e1?16 x e1 framers (496 time slots; time slot 0 not mapped)  sts-1 to ds3/e3 to 28 x ds1 (672 time slots)/21 x e1 (651 time slots)  28 x ds1?672 time slots  21 x e1?651 time slots  16 x e1?496 time slots  vt1.5?672 time slots  vt2.0?651 time slots  vt1.5 to ds1?672 time slots  vt2.0 to e1?651 time slots  tug-2 to ds1?672 time slots  tug-2 to e1 ? 651 time slots 4.7.7.2 overhead tsbus examples of the overhead ts bus operates at a data rate of 12.96 mbps. it carries pdh or sdh overhead communication chan nels and carries the data monitoring and data configuration for the device that communicates through tsbus interface with the cx28560. the data on the overhead tsbus is framed and consists of 84 time slots. the sources and destinations of overhead data transferred to and from the overhead tsbus are as follows: sonet/sdh section dccr?2 time slots line dccm?4 time slots spe path f2 user data?1 time slot spe path f3 user data?1 time slot spe n1 tandem connection?1 time slot ds3/e3 tdl overhead?1 time slot ds1 f-bits?1 time slot e1 si bits?1 time slot command status processor (csp)?13 time slots tsbus references for a detailed description of the tsbus interface, see cx29503 broadband access multiplexer (document #100702a), section 2.10.
28560-DSH-001-B mindspeed technologies? 4 - 15 advance information cx28560 data sheet cx28560 serial interface
4-16 mindspeed technologies? 28560-DSH-001-B advance information cx28560 serial interface cx28560 data sheet
28560-DSH-001-B mindspeed technologies? 5 - 1 advance information 5.0 the cx28560 memory organization the cx28560 interfaces with a system host by the transfer of data as fragments of packets over a dedicated data bus. the cx28560 also contains a set of internal registers that the host can configure over a pci bus, which control the cx28560. in addition, a unidirect ional flow control bus is used to monitor the amount of data in the cx28560?s internal transmit buffers. this s ection describes the various data headers, flow control packets and the layout of individual registers that are required for the operation of the cx28560. 5.1 memory architecture the cx28560 transfers data as fragments of packets prefixed with a fragment header. the fragments are transferred to the host over a dedicated data bus. configuration commands and monitoring info rmation are stored in a shared memory from which both the host and the cx28560 write and read. this assumes a system topology in which a host and the cx28560 both have access to shared memory for data control. the host allocates and de -allocates the required memory space. 5.1.1 register map and shared memory access during the cx28560's pci initialization, the system controller allocates a dedicated 1 mb memory range to the cx28560. the memory range allocated to the cx28560 must not map to any other physical or shared memory. instead, the system configuration manager allocates a logical memory address range and notifies the system or bus controllers that any access to these ranges must result in a pci access cycle. the cx28560 is assigned these addr ess ranges through the pci configuration cycle. once configured, the cx28560 beco mes a functional pci device on the bus. as the host accesses the cx28560's allocated address ranges, the host initiates the access cycles on the pci bus. it is up to individual the cx28560 devices on the bus to claim the access cycle. as th e cx28560's address ranges ar e accessed, it behaves as a pci slave device while data is being read or written by the host. the cx28560 responds to all access cycles where the uppe r 12 bits of a pci address match the upper 12 bits of the cx28560?s base address register (see chapter 2.0 , pci register 4, address 10h). for the cx28560, a 1 mb-memory space is assigned to the cx28560 base address register, which is written into pci configur ation space address 10h, register 4 in pci configuration registers. once a base address is assigned, a register map is used to access individual device resident registers. the cx28560 cannot respond to an access cycle that the cx28560 itself initiates as th e bus master. the register map provides the byte offset from the base address register where registers reside. the register map
5-2 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet layout is given in table 5-1 . it should be noted that there are two address spaces. the first one includes the registers that are di rectly accessed by the host through the pci (direct access) and the second includes th e registers that are accessed through the service request mechanism (indirect access). the only registers that can be directly accessed by the host as slave reads or writes are the rx port alive, the tx port alive, the interrupt status descriptor, the interrupt queue pointer, the interrupt queue length , the service request length, the service request pointer, and the soft reset registers. these are specified in table 5-1 . when the host writes directly into a corresponding register, the cx28560 behaves as a pci slave while this write is performed. all other registers need to be accessed through the service request mechanism. after the pci reset, when the cx28560 is ready for configuration, these registers are updated with the appropriate shared memory values through a configuration write service request. after the host has conf igured the shared memory image of the cx28560?s registers, and the cx28560 has finished its local configuration (i.e., srq_len bit field in service request length is reset to zero by the cx28560), the host issues a service request by writing directly into the service request length register. writing to this location the actua l value of the service request descriptor table length from shared memory caus es the cx28560 to start performing the service request descriptor table.
28560-DSH-001-B mindspeed technologies? 5 - 3 advance information cx28560 data sheet the cx28560 memory organization table 5-1. pci register map (direct access) register access type byte offset number of instances reset value receive port alive regi ster ro 00000h (bit) per port 0 transmit port al ive register ro 00004h (bit) per port 0 interrupt status register r/w 00008h per chip 0 interrupt queue pointer r/w 0000ch per chip 0 interrupt queue length r/w 00010h per chip 0 service request length re gister r/w 00014h per chip 0 service request pointer register r/w 00018h per chip 0 soft chip reset register wo 00020h per chip 0 note(s): 1. there are two address spaces: the first address space includes registers that are directly accessed by host through the pci. the second address space (shown in table 5-2 ) represents the cx28560?s register map access ible to the service request mechanism. therefore, all the registers shown in this table can be directly read or write by the host. 2. although the post reset value of the service requ est length is 0, until the cx28560 has finished all initializations, the value shown in the srq_len field of this register will be all 1s. pci configuration register 4 cx28560 base address register (bar) table 5-2. indirect register map address accessible via service request mechanism (1 of 2) register access type descriptor address (22 bits) number of instances reset value rbuffc flexifra me memory rw 000000?0053ff 21k per chip x rbuffc counter memory ro 008000?00bfff 8 per channel x rbuffc channel configuration regi ster rw 00c000?00c7ff 1 per channel x rbuffc data fifo size register rw 00fffb 1 per chip x rbuffc flexiframe control register rw 00fffc 1 per chip x rbuffc fragment size register rw 00fffd 1 per chip x rbuffc flexiframe slot time register rw 00fffe 1 per chip x rslp channel status register ro 050800?050fff 1 per channel x rslp channel configuration re gister rw 051000?0517ff 1 per channel x rslp maximum message length re gister 1 rw 053ffd 1 per chip x rslp maximum message length re gister 2 rw 053ffe 1 per chip x rslp maximum message length re gister 3 rw 053fff 1 per chip x rsiu ts/group map rw 094000?095fff 8k per chip x rsiu group map rw 096000?097fff 8k per chip x rsiu group map pointer allocation re gister rw 098000?0981ff 1 per group (512) x rsiu group state register rw 098200?0983ff 1 per group (512) x
5-4 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet it is critically important th at upon channel activation internal registers must be initialized. the cx28560 assumes the in formation is valid once a channel is activated. rsiu time slot/gr oup map pointer allocation regist er rw 09bfc0?09bfdf 1 per port x rsiu port configuration regi ster rw 09bfe0?09bfff 1 per port x tbuffc counter memory ro 0dc000?0ddfff 4 per channel x tbuffc channel configuration regi ster rw 0df000?0dffff 2 per channel x tbuffc flexifra me memory rw 0e0000?0e53ff 21k per chip x tbuffc data fifo size re gister rw 0e7ffc 1 per chip x tbuffc flexiframe control register rw 0e7ffd 1 per chip x tbuffc flexiframe slot time register rw 0e7ffe 1 per chip x tslp channel status regi ster ro 128800?128fff 1 per channel x tslp channel configuration re gister rw 129000?1297ff 1 per channel x tsiu ts/group map rw 16c000?16dfff 8k per chip x tsiu group map rw 16e000?16ffff 8k per chip x tsiu group map pointers register rw 170000?1701ff 1 per group (512) x tsiu group state register rw 170200?1703ff 1 per group (512) x tsiu time slot/group map pointer allo cation register rw 173fc0?173fdf 1 per port x tsiu port configuration regi ster rw 173fe0?173fff 1 per port x transmit pos-phy thresholds register rw 0e7ff9 1 per chip x transmit pos-phy control re gister rw 0e7fff 1 per chip x receive pos-phy control register rw 00ffff 1 per chip x ebus configuration register rw 1b4000 1 per chip x global configuration register rw 1b4001 1 per chip x these registers need to be accessed through the service request mechanism. table 5-2. indirect register map address accessible via service request mechanism (2 of 2) register access type descriptor address (22 bits) number of instances reset value
28560-DSH-001-B mindspeed technologies? 5 - 5 advance information cx28560 data sheet the cx28560 memory organization 5.2 global registers 5.2.1 service request mechanism the registers that need to be configured and checked to enable the activity of the service request mechanism are as follows:  service request length register (see table 5-1 )  service request pointer register (see table 5-1 ) the availability of the device is an exampl e of information provided by querying the service request length register. after the pci reset, the cx28560 sets the srq_len bit field in service request register to all ones until it performs all the internal initialization. when the cx2856 0 is finished with the internal initialization, it clears this field to 0. the cleared srq_len prov ides to the host the information of the cx28560?s readiness. from this point, the host is able to directly write this bit field with the actual number of service requests that the cx28560 needs to perform to configure its registers. the number of srqs written by the host is stored in the srq_len bit field. while processing th e service request commands, the srq_len field indicates how many commands are yet to be processed by the cx28560 before a new command can be issued. host slave writes to this register trigger the execution of the service request list. note: host slave writes to srq_len bit, while the previous list of service requests has not been processed (i.e., srq_len is reset) implies unpredictable behavior. table 5-3. service request length register bit field name value description 31:10 rsvd 0 reserved. 9:0 srq_len[9:0] ? serv ice request length. after a pci reset, host reads the srq_len bit field through pci slave access. while the srq_len value equals all 1s, the cx28560 is not ready to start the configuration of the device. if the cx28560 resets this value, the device is read y to be configured. host directly writes at this lo cation the number of service re quest descriptors (srd) which were allocated in service request descript or table (srdt) i.e. , shared memory. the srds used to be previously initialized and configured in srdt. this value represents the number of service request comm ands queued by host (i.e., th e srdt), that are waiting to be performed. real-time reads from srq_len provides th e number of service request commands that are waiting to be served.
5-6 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet the service request pointer register prov ides the address of the service request descriptor table (see table 5-4 ). host needs to allocate and initialize this table in shared memory. 5.2.1.1 service request descriptors a service request descriptor (srd) is a 4-dword location in shared memory. actually, one represents an entry in the srd table. the srd is defined as a union type in c, which allows different commands to be configured in a 4-dword space. the srd can handle three different configurat ions: device configuration descriptor (dcd), ebus configuration descriptor (ecd), and channel configuration descriptor (ccd). a list of service request commands is defi ned as a sequence of srds. the following instructions, referred to in the document as opcode, are supported:  configure a port/channel  read the cx28560 register or counters  expansion bus (ebus) read command  ebus write command  activate a channel  deactivate a channel  no-operation command table 5-5 defines the service request descriptor opcode. a service request is issued to a specific channel, or per whole device. on completion of each service request command, an acknowl edgment interrupt is generated (service acknowledge - sack) and sent to the host . this interrupt may be disabled per service request by setting the sackien bit of the srd to 0. it is possible for the host to issue multiple service requests successively with out expecting or receiving acknowledgments from each request if the sackien bit was not set accordingly in the srd. one mode of operation is for the host to se t the sackien bit in only the last srd so if a sack service request acknowledge interrupt is received, it will validate the whole list of service request commands. activate and deactivate commands could take a long time before they are actually executed by the cx28560. the cx28560 returns the sack (if sackien bit is set) immediately after it started the command execution. therefore, the host may not assume the command was actually executed just by detecting the sack was returned. another interrupt, end of command executio n (eoce), is defined for each of these commands. the host may assume the command was actually executed only after receiving the appropriate eoce. table 5-4. service request pointer register bit field name value description 31:3 srq_ptr[31:3] ? service request po inter. these 29 bits ar e appended with 000b to form a 32-bit address quadword aligned. this address points to the first entry on the service request descriptor table allocated in shared memory. 2:0 srq_ptr[2:0] 0 to ensure quadword alignment.
28560-DSH-001-B mindspeed technologies? 5 - 7 advance information cx28560 data sheet the cx28560 memory organization a similar situation arises when performing a change of flexiframe. the sack interrupt (if enabled) will be returned once the new flexiframe has been read into the cx28560?s internal memory. however the sy stem can only assume that the actual move to use the new flexiframe has been made once the rnfframe or tnfframe bit (see table 5-29 or table 5-44 ) has been set to zero or the nfframei interrupt has been received. table 5-5. service request descriptor?opcode description command value description nop 0h no operation. this service request performs no action other than to facilitate a host service acknowledge interrupt (sack). this would be used as a unix ping-like operation to de tect the presence of the cx28560. config_wr 1h configuration write. this is a request to copy from sh ared memory data into the cx28560? s internal registers. this service request can be issued for one or more consecutiv e registers, depending on the value of length bit field set in service request descri ptor. note: the service request desc riptor used for this command is device configuration descriptor. the length bit value in th is descriptor is up to 16 k. assuming that the host configures an 16 k register structure in shared memory and the length bit field will be set accordingly. note that over the pc i the configuration will be in burst s of 32 dwords (i.e., the maximum allowed pci burst). config_rd 2h configuration read. this is a request to copy the c onfiguration of the cx28560?s internal register(s) into shared memory. the configuration located at the a ddress specified by the cx28560 regist er map base addr ess offset is read and copied to the address spec ified by the shared memory addres s. the number of dwords copied is specified in the length bit fi eld. the user needs to instruct the cx28560 to perform the correct number of reads so that when data is written in shared memory, no data overlapping occurs. the service request descriptor us ed for this command is devi ce configurati on descriptor. ch_act 3h channel activation. this is a request to ac tivate a single channel. the cx28560 as sumes that the channel was already configured. if the channel is currently active, this command results in a destructive termination of the current message being processed, as well as flushing any other messages residing in the channel?s fifo. the service request descript or used for this command is ch annel configurat ion descriptor. ch_deact 4h channe l deactivation. this is a request to deactivate a channel. this command results in a destructive termination of the current message being processed, as well as flushing of any other messages residing in the channel?s fifo. the srd used for this command is channel configuration descriptor. rsvd 5h reserved. ebus_wr 6h ebus write. this is a request to execute write transaction(s) over the ebus. data is copied from host memory to the ebus. ebus_rd 7h ebus read. this is a request to execute read transaction(s) over the ebus. data is copi ed from the ebus address specified in the 3rd dword of ebus configuration desc riptor to the shared memo ry location specified in the 2nd dword of ebus configuration descriptor. the data length copied from one location to another location is specified by length bi t field in ebus configuration d escriptor. note: the ebus_rd and ebus_wr service request mechanism allow a maximum of 16 k dwords transfer to/from the ebus. the transaction is split to bursts of 32 dwords over the pci. rsvd 8h?1fh reserved.
5-8 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.2.1.2 service request descriptors each srd is 4 dwords. the srds used by the cx28560 are as follows:  device configuration descriptor (dcd)  ebus configuration descriptor (ecd)  channel configuration descriptor (ccd) device configuration descriptor (dcd) table 5-6 presents the structure of dcd. table 5-7 describes these fields. ebus configuration descriptor (ecd) table 5-8 presents the ebus configuration service request descriptor. table 5-6. device configuration descriptor dword number bit 31 bit 0 dword 0 opcode[31:27] sackien[26] reserved[25:14] length[13:0] dword 1 shared memory pointer 00 dword 2 reserved[31:24] indirect register map address[23:2] 00 dword 3 reserved table 5-7. dcd field descriptions descriptor field size description opcode 5 command requested by th e host. (config_wr, config_rd) sackien 1 0 = sack interrupt disabled. 1 = sack interrupt enabled. an appropriate interrupt is ge nerated after the command is completed. length 14 number of double words in the memory transaction request. if ?0? the number of transfers is 16 k. therefore, it allows fo r any number of dwords from 1?16384. shared memory pointer 30+2 shared memory base address fo r a memory transaction requ est. the pointer is dword aligned by concatenating two zeros to the lsb and making it a 32b pointer. indirect register map address 22 the register address for the co nfiguation read or write request. table 5-8. ebus configuration service request descriptor dword number bit 31 bit 0 dword 0 opcode[31:27] sackien[26] reserved[25:19] incdis[18] byte enable[17:14] length[13:0] dword 1 shared memory pointer 0 0 dword 2 ebus base dword 3 reserved
28560-DSH-001-B mindspeed technologies? 5 - 9 advance information cx28560 data sheet the cx28560 memory organization table 5-9 describes these fields. channel configuration descriptor (ccd) table 5-10 presents the structure of ccd. table 5-11 describes these fields. table 5-9. ecd field descriptions descriptor field size description opcode 5 command requested by the host. (ebus_wr, ebus_rd) sackien 1 0 = sack in terrupt disabled. 1 = sack interrupt enabled. length 14 number of double words in the memory transaction request.. byte enable 4 determines which byte la nes carry meaningful data. be [0] applies to byte 0 (lsb). be[3] applies to byte 3 (msb). these bits are active high, i.e. ?1? indicates enable, ?0? indicates disable incdis 1 disable ebus address incrementing for fifo access. when this bit is set, the cx28560 will access the same address lengt h times (fif o access). when this bit is zero, the cx285 60 will automatically incremen t the address transmitted by one for each access performed (i.e., final address will be ebus base address + length ? 1). shared memory pointer 30 + 2 the address of shared memory eb us base address, where the c onfiguration of local devices exists. the pointer is dword aligned (l ast 2 bits should be set to zero). ebus base address 32 ebus base (byte ali gned) address for an ebus transaction. table 5-10. channel configuration service request descriptor dword number bit 31 bit 0 dword 0 opcode[31:27] sackien[26] re served[25:12] rx/tx[11] channel[10:0] dword 1 reserved dword 2 reserved dword 3 reserved table 5-11. ccd field descriptions descriptor field size description opcode 5 command requested by the host. (ch_act, ch_deact, nop,) sackien 1 0 = sack interrupt disabled. 1= sack interrupt enabled ? after completion of the command, a service acknowledge (sack) interrupt will be generated. channel 11 channel number. this field is interpreted as a ch annel number for the ch_act and ch_deact commands. the field is interpreted as reserved for the nop command. tx/rx 1 0 = the command is for a receive channel. 1 = the command is for a transmit channel. rsvd ? reserved.
5-10 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.2.2 port alive registers the receive and transmit port alive register s are read-only registers. these registers can only be accessed via direct pci transaction. each bit of the receive and transmit port alive register represents th e device port number. refer to table 5-12 and table 5-13 for these registers. these registers operate as a gate which en ables or disables the access to the port configuration register. if the corresponding bit of the receive and transmit port alive register is set, a new port configuration for the specified port is allowed. after a pci reset or software chip reset, a ll 32 bits of the receive and transmit port alive register are cleared (set to 0). e ach bit is automatically set to 1 after 24 ? 32 serial clock cycles occur on that specific port. after the corresponding bit is set to 1, the host can write to the port configuration register. the host cannot program a new port configuration until the corresponding bit/port is set to 1 in the port alive register depending upon the direction of receive or transmit. a proper configuration sequence for accessing the port configuration register is as follows: 1. host polls the port alive register for the specific port/direction and waits (24? 32 serial clock cycles) until the corresponding bit in the port alive register is set (the polled bit is one). 2. host issues a service request (srq) port configuration command and waits for a service request acknowledge (sack). 3. host gets the sack. note: writing to the port configuration register causes the corresponding bit from the port alive register to be cleared. this bit is automatically set to 1 after 24 ? 32 serial clock cycles occur; therefore, a new port configuration will be allowed. 4. host checks if a new port configur ation is allowed by checking the corresponding bit in the port alive register. go to 1. 5.2.3 soft chip reset register this register contains 1 bit. any write of an y value to a soft chip reset (scr) generates a soft reset for the cx28560. an scr affect s the cx28560 exactly as pci reset, except that the pci block is not reset. no pci configuration is performed after a scr. table 5-12. receive port alive register bit field name value type description 31:0 rpa[31:0] ? ro this register controls the access to the receive port configurat ion register. if one of the 32 bits is set, then the receive port conf iguration for that specific port is allowed. table 5-13. transmit port alive register bit field name value type description 31:0 tpa[31:0] ? ro this register contro ls the access to the transmit port configuration register. if one of the 32 bits is set, then the transmit po rt configuration for that specific port is allowed.
28560-DSH-001-B mindspeed technologies? 5 - 11 advance information cx28560 data sheet the cx28560 memory organization 5.3 interrupt level descriptors the cx28560 generates interrupts for a variet y of reasons. interrupts are events or errors detected by the cx28560 during pr ocessing of the incoming serial data streams. interrupts are generated by the cx28560 and forwarded to the host for servicing. the cx28560 gathers the many events and er rors (generated by all units such as rbuffc and tbuffc, rslp and tslp, and siu) and notifies the host over the pci. interrupt descriptors are generated by the cx28560 and forwarded to the host for servicing. individual types of interrup ts may be masked from being generated by setting the appropriate interrupt mask or interrupt disable bit fields in various descriptors. the interrupt mechanism, e ach individual interrupt, and interrupt controlling mechanisms are discussed in this section. 5.3.1 interrupt queue register the cx28560 employs a single interrupt queue register to communicate interrupt information to the host. this register is stored within the cx28560. this register stores the location and the si ze of an interrupt queue (user configurable) in allocated shared memory where the interrupt descri ptors will be directly placed by the cx28560 while acting as a pci bus master. the cx28560 requires this information to transfer interrupt descriptors to shared memory. all the interrupts are processed by the host, in an interrupt service routine (isr ). the cx28560's pci interface must be configured to allow bus mastering. the interrupt queue register (i.e., interrupt queue po inter and interrupt queue length) is initialized by the host via a direct pci write transaction. after a pci reset or software chip rese t (scr), the interrupt queue pointer is the first register that needs to be initialized. a typical in itialization procedure is as follows: 1. the host writes in the interrupt queue pointer register allocated by performing a direct write to the address of th e interrupt queue in shared memory. 2. the host writes in the interrupt queue le ngth by performing a direct write to this location, the value of the interr upt queue length allocated in shared memory. note: the user can change, at any time, the length of the interrupt queue (iqlen field in the interrupt queue length re gister) or the pointer value of the interrupt queue pointer (iqptr field in the interrupt queue pointer register). however, writing to these registers while the chip is operating may result in flushing the interrupts held in the internal fifo.
5-12 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.3.1.1 interrupt descriptors the interrupt descriptor describes the format of data transferred into the queue. there are two different types of the interrupt descri ptor. the first type is used to represent buffc's block related interrupts and the second type is used to represent other interrupts. both types are 64-bit fields. gene rically, the interrupt descriptor includes fields for:  identifying the source of interrupt from within the cx28560 channel causing the interrupt (1-2047) and di rection (receive or transmit)  events assisting the host in synchronization channel, port and independent activities  errors and unexpected conditions result ing in lost data, discontinued message processing, or prevented successful completion of a service request all the interrupts are associated with a ch annel or direction with the following four exceptions: 1. when an oof or cofa condition is detected on a serial port, only one interrupt is generated for the port un til the condition is cleared and the condition reoccurs. table 5-14. interrupt queue pointer bit field name value description 31:3 iqptr[31:3] ? shared memory interrupt queue pointer these 29 bits are appended with 000b to form a 64-bit aligned addres s. this address points to the first entry (quad-word) of the interrupt queue buffer. the host can change this field while the chip is operating. however, this re sults in flushing all interrupts residing in the internal interrupts fifo. 2:0 iqptr[2:0] 0 ensures 64 bit alignment table 5-15. interrupt queue length bit field name value description 31:15 rsvd 0 reserved 14:0 iqlen[14:0] ? shared memo ry interrupt queue length this 15-bit number specifies the length of the interrupt queue buffer in quad-words (i.e., the number of descriptors in the queue). note(s): 1. the host may change this field while the ch ip is operating. howe ver, this results in flushing all interrupts residing in the internal interrupts fifo. after reset, iqlen is set to 0. this has the effect of blocking all the interrupt processing by the cx28560.
28560-DSH-001-B mindspeed technologies? 5 - 13 advance information cx28560 data sheet the cx28560 memory organization 2. the ilost interrupt bit indicates that an interrupt has been lost internally when the cx28560 generates more interrup t descriptors than can be stored in the interrupt queue in shar ed memory. the latency of host processing of the interrupt queue (handling the interrupts in the irs) can be a factor in this, as can the length of the actual queue. this condition is convey ed by the cx28560 overwriting the ilost bit field in the last interrupt descriptor in the internal queue prior to being transferred out to shared memory. the bit field is not specific to or associated with the interrupt descriptor being overwritten. only one bit is overwritten and the integrity of the original descriptor is maintained. 3. the perr interrupt bit indicates that a parity error was detected by the cx28560 during a pci access cycle. this condition is conveyed by the cx28560 overwriting the perr bit field in the last interrupt descriptor in the internal queue prior to being transferred out to shared memory. the bit field is not specific to or associated with th e interrupt descriptor being overwritten. only one bit is overwritten and the integrity of the original descriptor is maintained. 4. the poserr interrupt indicates that either a pos-phy buffering error occurred (underrun or overflow), or that a parity error was detected on the data in bus (cx28560?s transmit data pos-phy bus). the cx28560 has two types of interrupt descriptor. one is the buffc interrupt descriptor, the other is the non-buffc interrupt descriptor. the following items describe the errors/e vents reported in the buffc interrupt descriptor:  rxeom (receive end of message). this interrupt is accompanied by a message status - rxerr (errored me ssage coding). th e message status included in an interrupt can be one of the following: ? rxnoerr ? no errors in the message ? rxfcs ? frame check sequence error ? rxbuff ? overflow ? rxcofa ? change of frame alignment ? rxoof ? out of frame ? rxabt ? abort frame ? rxlng ? long message ? rxalign ? byte alignment error  rxeoc/txeoc (receive/transmit end of command execution). the rbuffc or tbuffc has completed the activation/deactivati on of a channel.  rxnfframei/ txnfframei (rec eive/transmit change to new flexiframe indication). the cx28560 receive/transmit buffc has completed the transition to the new flexiframe.  rxshrt (receive too short message).  rxposerr/txposerr (rece ive/transmit error).  ilost (interrupt lost).
5-14 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet the following items describe the errors/eve nts reported in the non-buffc interrupt descriptor.  rxbuff/txbuff (receive and transm it buffer errors underrun and overflow)  txeom (transmit end of message)  rxchabt (receive change to abort)  rxchic (receive change to idle)  rxcofa/txcofa (receive and tran smit change of frame alignment)  rxcrec/txcrec (receive and transmit cofa recovery)  rxoof (receive out of frame)  sackerr (service acknowledge error, an attempt to access an illegal address within the cx28560)  rxfrec/rxsport (receive frame recovery, receive serial port interrupt) buffc interrupt descriptor format the buffc interrupt descriptor is 64 bits wide, and the detailed description of its fields is provided in table 5-16 . the most significant bit in the buffc interrupt descriptor is always read as 0. table 5-16. buffc interrupt descriptors format (1 of 3) bit field name value description 63 typ 0 interrupt de scriptor?type 0. 62:58 rvsd ? reserved. 57:47 ch[10:0] ? channel numbe r causing the interrupt. 46:43 rvsd ? reserved. 42 dir 0 direction?rx. 1 direction?tx. 41 rvsd reserved. 40 rxeom/txbovflw 0 n o receive end of me ssage occurred. no transmit channel internal overflow occurred. 1 if dir = 0 (receive)?an end of message occurred, even if errors were detected (rxeom) and the rxerr field is relevant. if dir = 1 (transmit)?a channe l?s internal buffer overflowed. 39 rxeoc/txeoc 0 end of command exec ution interrupt was not generated. 1 the rxeoct/txeoct field is relevant. if dir = 0 (rx)?end of command exec ution interrupt occurs (rxeoc). if dir = 1 (tx)?end of command exec ution interrupt oc curs (txeoc). 38 rxeoct/txeoct 0 end of command type?deactivate. this bit is only relevant if rxeoc/txeoc is set. 1 end of command type?activate. this bit is only relevant if rxeoc/txeoc is set.
28560-DSH-001-B mindspeed technologies? 5 - 15 advance information cx28560 data sheet the cx28560 memory organization 37 rxnfframei/txnfframei 0 transition to the new flexiframe has not been completed. 1 transition to the new flex iframe has been completed. if dir = 0 then this is a rnfframei, otherwise if dir = 1 then this indicates a tnfframei. the channel num ber field is not valid. 36:35 rvsd ? reserved 34:32 rxerr[2:0] end of message status decoding. note(s): this field is only valid if dir = 0 and rxeom = 1. 0 receiver message error (decoded) - no error. 1 rxbuff = overflow 2 rxcofa = change of frame alignment. 3 rxoof = out of frame. 4 rxabt = abort termination. generated when received message is terminated with an abort sequence (at least seven se quential ones). 5 rxlng = long message. generated when received message length (after zero extraction) is greater than selected maximum message size (depended on rslp maximum message length registers). message reception is terminated and further transfer of data to the host is not performed. 6 rxalign = byte alignment error. generated when message payload size, after zero extraction, is not a multiple of 8 bits. this generally occurs with a fcs error. this interr upt also implies a fcs error. the fcs interrupt will not be generated if the align interrupt is issued. 7 rxfcs = frame check sequence error. generated when received hdlc frame is terminated with byte aligned 7eh flag but computed fcs doe s not match received fcs. 31:27 rvsd ? reserved. 26 rxshrt/txrsvd 0 a receiv e too short message inte rrupt was not generated. 1 if dir = 0 (rx)?rx s hort message occurs. if dir = 1 (tx)?reserved table 5-16. buffc interrupt descriptors format (2 of 3) bit field name value description
5-16 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 25:24 rxposerr/txposerr 00 no pos- phy error (receive & transmit). 01 receive: pos phy error (from urx) ------ transmit: flow conductor pos phy buffer overflow. the channel number field is not valid. 10 receive: reserved ------- transmit: data pos phy error (d ue to assertion of error line) 11 receive: reserved ------- transmit ? data pos phy fatal error. caused by the detection of either a parity error or the overflow of a pos- phy internal buffer. the channel number field is not valid. 23:1 rsvd 0 reserved 0 ilost 0 no interrupts have been lost. 1 interrupt lost. generated when internal interrupt queue is full and more interrupt conditions are detected. as the cx28560 has no wa y to store the newest interrupt descriptors, it discards the new interrupt s and overwrites this bit in the last interrupt in an internal que ue prior to that interrupt being transferred out to shared memory. the integrity of th e descriptor bein g overwritten is maintained completely. table 5-16. buffc interrupt descriptors format (3 of 3) bit field name value description
28560-DSH-001-B mindspeed technologies? 5 - 17 advance information cx28560 data sheet the cx28560 memory organization non-buffc interrupt descriptor format the non-buffc interrupt descriptor is 64 bits wide, and the detailed description of its fields is provided in table 5-17, non-buffc interrupt descriptors format . the most significant bit in the non-buffc inte rrupt descriptor is always read as 1. table 5-17. non-buffc interrupt descriptors format (1 of 2) bit field name value description 63 typ 1 interrupt de scriptor?type 1. 62:58 rsvd ? reserved 57:47 ch [10:0] ? channel number causing the interrupt 46:43 rsvd 0 reserved 42 chdir 0 receive channel interrupt. 1 transmit channel interrupt. 41 rxbuff/txbuff ? buffer error. data is lost. the cx28560 has no place to re ad or write data internally. if from transmitter, then internal buffer underrun. if fr om receiver, internal buffer overflows. 40:38 rsvd 0 reserved 37 rxrsvd/ txeom ? receive: reserved transmit: end of message. 36:34 rsvd 0 reserved 33 rxchabt/txrsvd ? receive : change to abort code set to one when the received pad f ill code changes from 7eh to all ones --------------- transmit: reserved. 32:30 rsvd 0 reserved 29 rxchic/txrsvd ? receive: change to idle code set to one when a received pad fill code changes from all ones to 7eh --------------- transmit: reserved. 28:25 rsvd 0 reserved 24:20 prt [4:0] ? port number causing the interrupt. 19:18 rsvd 0 reserved 17 prtdir 0 receive port interrupt. 1 transmit port interrupt. 16 rxcofa/txcofa ? change of fram e alignment. set to one when a cofa condition is detected. 15 rxoof/txrsvd ? receive: out-of-frame. set to one when serial port is configur ed in channelized mode and receiver-out-of-frame (roof) i nput signal assertion is detected. --------------- transmit: reserved. 14 rxfrec/txrsvd ? receive: frame recovery. set to one when serial port transitions fr om out-of-frame (oof ) back to in-frame. ------------- transmit: reserved.
5-18 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 13 rxcrec/txcrec ? receive: cofa recovery. --------------- transmit: cofa recovery. set to one when serial port transitions from cofa back to in-frame. 12:4 rsvd 0 reserved 3 sack status sack status bit. only valid if the sack bit is asserted. 0 no error on exit. 1 service acknowledge error occurred. an attempt was ma de to access an illegal address. an illegal address is one that is not defined in any of the memory map registers. 2 sack ? buffc service acknowledge. set to one at conclusion of hos t service, which was processed successfully. in case of an error being executed as a result of a host service, other interrupts may be generated ? perr , for example. 1 perr 0 no pci parity erro rs have been detected. 1 pci bus parity error. generated when the cx28560 dete cts a parity error on data being transferred into the cx28560 either from another pci agent writing into the cx28560 or from the cx28560 reading from shared memory. this e rror is specific to the data phase (non- address cycle) of a pci tran sfer while the cx28560. pci sy stem error si gnal, serr*, is ignored by the cx28560. to mask the perr interrupt, the cx28560's pci configuration space, f unction 0, register 1, parity er ror response field must be set to 0. 0 ilost 0 no interrupts have been lost. 1 interrupt lost. generated when internal in terrupt queue is full and mo re interrupt conditions are detected. as the cx28560 has no way to stor e the newest interrupt descriptors, it discards the new interrupts and overwrites this bit in the la st interrupt in an internal queue prior to that interrupt being transfer red out to shared memory. the integrity of the descriptor being overwritte n is maintained completely. table 5-17. non-buffc interrupt descriptors format (2 of 2) bit field name value description
28560-DSH-001-B mindspeed technologies? 5 - 19 advance information cx28560 data sheet the cx28560 memory organization 5.3.1.2 interrupt status register the interrupt status register is located in a fixed position in the cx28560?s internal register. the cx28560 updates this register after each transfer of interrupt descriptors from its internal queue to the interrupt queu e in shared memory. th e host is required to read this register from the cx28560 before it processes any interrupts. the contents of the interrupt status register are reset on hardware reset or soft chip reset or whenever any field in the interr upt queue register is modified. note: this internal register is directly accessed by the host. table 5-18. interrupt status register bit field name host access value description 31 mstrabt r ? master abort. when the cx28560 encounters a pci abort while operating as a pci master, it does not attempt to recover from this error. in this case the cx28560 asserts the serr* signal, a nd the mstrabt bit and waits for the host to reset (i.e., pci reset or soft reset). this bit is asserted when the target does not assert devsel within a specific pclk cycles or when the target terminates a transaction in which the cx28560 is the master, with an abort (i.e., assertion of stop# with a deassertion of devsel) sequence. 30:16 wrptr 14:0] r ? write interrupt pointer. 15-bit quadword index from start of interrupt queue up to where the cx28560 is going to insert the next interrupt descriptors. the host may read this value to get the location of the last descriptor, which was not served yet, in the queue. as the queue is circular, care must be taken to ensure roll over at beginning a nd end of queue. only the cx28560 updates this value. the wrpt r is a read only bit field. 15 intfull r 0 1 interrupt queue not full?shared memory. interrupt queue full?shared memory. the host writing any value to the rdptr clears the intfull status bit. 14:0 rdptr[14:0] r/w ? read interrupt pointer. 15-bit quadword index from start of interrupt queue up to where the host first unread interrupt descriptor resi des. the host may read this value to get the location of the first descriptor , which was not served yet, in the queue. as the queue is circular, care mu st be taken to ensure roll over at beginning and end of queue. only th e host updates this value. the rdptr is a read/write bit field. note(s): writing the value of the rdptr automatically resets the intfull status bit. therefore, if the value written into rdptr is the same value as was read from this field, it is assumed that the host has read all the interrupt descriptors.
5-20 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.3.2 interrupt handling 5.3.2.1 initialization interrupt management resources are au tomatically reset upon the following: hardware reset soft reset write to interrupt queue poin ter by a direct pci write write to interrupt queue length by a direct pci write the cx28560 uses two interrupt queues. one is internal to cx28560 and is controlled exclusively by the dma block. the other is the interrupt queue in shared memory, which is allocated and administered by the host, and written to (filled) by the cx28560. upon initialization, the data in the status descriptor is reset to all 0s, indicating the first location for next descri ptor, the queue is not full, and no descriptors are currently in the queue. any existing descriptor s in the internal queue are discarded. the host must allocate sufficie nt shared memory space for the interrupt queue. up to 64 k dwords of queue space are accessible by the cx28560, setting the upper limit for the queue size. the cx28560 requires a minimum of two quadwords of queue space. this sets the lower limit for the queue size. the host must store the pointer to the queue and the length in quadwords of the queue in the cx28560 within the interrupt queue descriptor registers. issuing the appropriate host service to the cx28560 can do this. as the cx28560 takes in the new values, it automatically resets the controller logic as indicated above. this mechanism can also be used to switch interrupt queues while the cx28560 is in full operation. 5.3.2.2 interrupt descriptor generation interrupt conditions are detected in both error and non-error cases. cx28560 makes a determination based on channel and device configuration whether reporting of the condition is to be masked or whether an interrupt descriptor is to be sent to the host. if the interrupt is not masked, cx28560 generates a descriptor and stores it internally prior to transferring it to the interrupt queue in shared memory. the internal queue is capable of holding 512 descriptors while cx28560 arbitrates to master the pci bus and transfer the descri ptors into the interr upt queue in shared memory. as the pci bus is mastered and after desc riptors are transferre d out to the shared memory, cx28560 updates the interrupt status descriptor. when cx28560 updates the wrptr field in the interrupt status descriptor, it asserts the pci inta# signal line. if during the transfer of descriptors, the interrupt queue in sh ared memory becomes full, cx28560 stops transferring descriptors until the host indicates more descriptors can be written out. cx28560 indicates that it cannot transfer more descriptors into shared memory by setting the bit field in tfull in the interrupt status descriptor. in cases where the internal queue is full (eith er because the host queue is full or there was not enough pci bandwidth) and ne w descriptors are generated, the new descriptors are discarded. cx 28560 indicates it has lost interrupts internally by overwriting the bit field ilost in the last interrupt descriptor in the internal queue. the ilost indication represents one or more lost descriptors.
28560-DSH-001-B mindspeed technologies? 5 - 21 advance information cx28560 data sheet the cx28560 memory organization 5.3.2.3 inta# signal line the host must monitor the inta # signal line at all times. an assertion of this line signifies the updating of the wrptr fiel d in the interrupt status descriptor, indicating that interrupt descriptors have be en transferred to th e interrupt queue in shared memory from the internal interrupt queue. upon detection of the inta# assertion, the host must perform a direct read of the interrupt status descriptor from within cx28 560. this descriptor provides the offset to the location of the first descriptor in th e host queue that has not been served, the offset to the location of the last descriptor serviced by the host, and the determination if the queue is full. the inta* signal is deasserted on each read of the interrupt status descriptor. the host applies its interrupt service routines to service each of the descriptors. as the host finishes servicing a number of de scriptors, it must writ e the offset to the location of the last serviced descriptor b ack into the rdptr fi eld of the interrupt status descriptor. a write to this field indicates to cx28560 that the descriptor locations, which were waiting to be serviced, have been serviced and new descriptors can be written. figure 5-1 illustrates the operation of inta*. figure 5-1. interrupt notification to host note: cx28560 continues to write to availa ble space regardless of whether the host updates the rdptr field. the difference between the two interrupt queue pointers rdptr and wrptr indi cates the number of interrupts still need to be serviced. when cal culating the number of outstanding interrupts, please make sure to take care of offsets, or pointers, wraparound. internal logic unserviced interrupt descriptors in the interrupt queue cx28500 host memory interrupt handler interrupt queue inta* 500052_056
5-22 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.4 global configuration register the global configuration register specifies configuration informa tion applying to the entire device. this register must be progra mmed before any channel is activated. the only field in this register that can be ch anged while the chip is operating (i.e., not immediately after reset) is the pci_en field. the components and their descriptors are given in table 5-19 . table 5-19. global configuration register bit field name value description 31:14 rsvd 0 reserved 13 pos-phy_reg 0 pos-phy non-regi stered mode (normal mode). the rxenb/frenb signa l will be sampled according to the pos-phy standard. 1 pos-phy registered mode. the rxenb/frenb si gnal will be sampled one clock cy cle later than defined in the pos-phy standard. 12 rsvd 0 reserved 11 pci_target_fbtb 0 use the fast back -to-back feature as c onfigured in the pci configuration settings. 1 the cx28560 as pci master attempts to fa st-back-to-back the pci transaction to other targets regardless of pci configuration settings. this bit is defined to force the cx28560?s fast back-to-back ca pability regardless of the pci configuration. the pci specification states that if there is a single device in th e system that does not support a fast back-to-back transaction as a target , the fast back-to-back mode is disabled. setting this bit to 1 instructs the cx28560 to ignore the pci configuration settings and execute fast back-to-back transactions when appropriate according to the pci specification. the host can se t this bit only if the cx 28560 is always accessing the same target which is capable of fast back to back transactions. this is not a violation of the pci specification, ra ther it is an implementati on of an allowed behavior. 10 pci_br 0 little-endian storag e convention (intel-style). the least significant byte to be stored in and retrieve d from the lowest memory address. 1 big-endian storage convention (motorola-style). an example of little-big endian byte ordering is shown in appendix e. 9:1 rsvd 0 reserved 0 pci_en 0 pci interrupt disabl ed?global interrupt mask. 1 pci interrupt enabled note(s): 1. after reset, the value of globa l configuration register is 0.
28560-DSH-001-B mindspeed technologies? 5 - 23 advance information cx28560 data sheet the cx28560 memory organization 5.5 ebus configuration register the ebus configuration descriptor, defined in table 5-20 , specifies the configuration parameters for ebus transactio ns. the host must configure this register before any attempt to access the ebus. table 5-20. ebus configuration register bit field name value description 31:13 rsvd 0 reserved. 12 mpusel 0 1 expansion bus microprocessor selection motorola-style. expansion bus supports the motorola-style mi croprocessor interface and uses motorola signals: bus request (br*), bus grant (bg*), address st robe (as*), read/write (r/wr*), and data strobe (ds*). expansion bus microprocesso r selection? intel-style. expansion bus supports the intel- style microprocessor interface and uses intel signals: hold request (hold), hold acknowledge (hlda), address latch enable (ale*), write strobe (wr*), and read strobe (rd*). 11 ecken 0 1 expansion bus clock disabled. eclk output is three-stated. expansion bus clock enabled. the cx28560 re-drives and inverts pclk input onto eclk output pin. 10:8 alapse[2:0] ? expansion bus address duration. the cx28560 extends the duration of valid addr ess bits during an ebus address phase to alapse+1 number of eclk peri ods. the control lines ale* (i ntel) or as* (motorola) indicate that the address bits have had the desired set-up time. 7:4 blapse[3:0] ? expansion bus access interval. the cx28560 waits blapse number of eclk periods imme diately after re linquishing the bus. this wait ensures that all the bus grant signa ls driven by the bus arbiter have sufficient time to be de-asserted as a result of bus request signals being de-asserted by the cx28560. 3:0 elapse[3:0] ? expansion bus data duration. the cx28560 extends the duration of valid da ta bits during an ebus data phase to elapse + 1 number of eclk peri ods. the control lines rd* and wr* (intel) or ds* and r/ wr* (motorola) indicate the data bi ts have had the de sired setup time. note(s): (1) after reset, the value of ebus configuration register is 0.
5-24 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.6 pos-phy control registers 5.6.1 transmit pos-phy thresholds register the transmit pos-phy control register prov ides the necessary parameters for flow control on the pos-phy interface. 5.6.2 transmit pos-phy control register this register controls the parameter necessary to make the pos-phy work. table 5-21. transmit pos-phy thresholds register bit field name value description 31 disblpar 0 1 data arriving on the transm it pos-phy will be checked for correct parity. parity checking is disabled. 31:25 rsvd 0 transmit pos-phy thresholds. 24:16 tptpahith ? ptpa high threshold. above this number of dwords (4 bytes) in the buffer, th e bus request is deasserted. 15:9 rsvd 0 reserved 8:0 tptpalowth ? ptpa low threshold. below this number of dwords (4 bytes) in the buffer, the bus request is asserted. table 5-22. transmit pos-phy control register bit field name value description 31:3 rsvd 0 reserved. 2 tposbufffullien 0 pos-phy buff er full interrupt disabled. 1 pos-phy buffer full interrupt enabled. on encountering full pos-phy buffers, an interrupt will be generated. 1 tpparerrien 0 pos-phy parity error interrupt disabled. 1 pos-phy parity error interrupt enabled. on detection of a parity bit error, a pa rity error interrupt will be generated. 0 tperrien 0 pos-phy erro r interrupt disabled. 1 pos-phy error in terrupt enabled. when the pos-phy error pin is assert ed an interrupt will be generated.
28560-DSH-001-B mindspeed technologies? 5 - 25 advance information cx28560 data sheet the cx28560 memory organization 5.6.3 receive pos-phy control register this register controls the parameter n ecessary to make the pos-phy work. it determines whether an interrupt will be generated when the rbuffc encounters the situation that it tries to send data to the pos-phy, but there is no room in the pos- phy buffer. this register is set once for the chip. table 5-23. receive pos-phy control register bit field name value description 31:1 rsvd 0 reserved. 0 rposbufffullien 0 pos-phy buffer full interrupt disabled. 1 pos-phy buffer full interrupt enabled. on encountering full pos-phy buffers, an interrupt will be generated.
5-26 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.7 receive path registers receive path registers contain the information necessary to configure the receive direction. this configuration includes regi sters that are related to the buffc block, host interface, registers that control the rslp, and rsiu. 5.7.1 rslp channel status register the rslp channel status register is a read only (ro) register. it provides information from rslp block regarding the channel state. there is one rslp channel status register for each of the cx28560?s channels (i.e., 2047 registers). 5.7.2 rslp channel co nfiguration register the receive channel configuration register contains configuration bits applying to the logical channels w ithin the cx28560. there are 2047 such registers, one for each channel. the rslp channel co nfiguration register configures aspects of the channel common to all messages passing through the channel. one descriptor exists for each logical channel direction. table 5-25 lists the values and desc riptions of each channel configuration descriptor. for each channel to be used in the cx28560, this register must be configured before activa tion (no default values exist). table 5-24. rslp channel status register bit field name host value description 31:1 rsvd r ? reserved. 0 ractive r 0 1 channel inactive. the channel has been deactivated due to either a service request channel deactivation or reset (pci reset or soft chip reset). channel active. the channel has been activated by service request channel activation table 5-25. rslp channel configuration register (1 of 2) bit field name value description 31:30 rprotcol[1:0] 0 transparent. 1 hdlc with no fcs. used in rslp for full packet forwarding and/ or channel monitoring application. for this mode the short message detect ion is disabled. any number of bytes can be transmitted and received within any single messag e including messages of only one byte. 2 hdlc with fcs16 (fcs?2 bytes). 3 hdlc with fcs32 (fcs?4 bytes). 29 rinv 0 data inversion disabled. 1 data inversion enabled. message is received fr om siu with polarity change (the inversion is done to all bits received).
28560-DSH-001-B mindspeed technologies? 5 - 27 advance information cx28560 data sheet the cx28560 memory organization 28:21 rmask_sb[7:0] ? data mask. only bits with a value of 1 contain relevant data (e.g., mask = 10000001, then only bits 0 and 7 contain channel's data). enables the sub-channeling feat ure. note 0h is an invalid value. 20:5 rsvd 0 reserved. 4:3 rmaxsel[1:0] 0 message length check disabled. 1 message length check enabled. use maxfrm1 bit field in the message lengt h descriptor for maximum receive message length limit. 2 message length check enabled. use maxfrm2 bit field in the message length descriptors maximum receive message length limit. 3 message length check enabled. use maxfrm3 bit field in the message lengt h descriptor for maximum receive message length limit. 2 rfcstrans 0 fcs transfer normal. do not transfer receiv ed fcs to the host along with data message. 1 non-fcs mode. transfer received fcs to the host along wi th data message. in non-fcs mode short message detection is disabled. 1 rbuffien 0 overflow interrupt disabled. 1 overflow interrupt enabled. 0 ridleien 0 chabt, chic, sht interrupt disabled. 1 chabt, chic, sht interrupt enabled. when the rslp detects a change to abort or a change to idle code, the relevant interrupt is generated. setting this bit to 1 is also necessary if the too short counter in the rbuffc is to be used. table 5-25. rslp channel configuration register (2 of 2) bit field name value description
5-28 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.7.3 rslp maximum message length register the rslp maximum message length register, defined in table 5-26 , can have three separate values for maximum message length: maxfrm1, maxfrm2, and maxfrm 3. their structure is shown in rslp channel configuration register. th e minimum message length is either 1, 3, or 5 depending on protocol mode: no fcs, 16-bit fcs, or 32-bit fcs, respectively. in the case of a short message, data is not transferred to the host but instead is discarded. in addition, an interrupt descriptor is generated toward the host indicating the short error condition. note, a bit stream that contains messages of length less than 40 bytes requires the cx28560 to be configured with large buffers. although the cx28560 can work with small messages, the bu ffer calculations and bandwidth calculations have to be re-examined. each receive channel either selects one of these me ssage length values or disables message length checking altogether. the maxsel bit field (see table 5-25 ) selects which (if any) register is used for received message length checking. if the cx28560 receives a message exceeding the allowed maximum, the current message processing is discontinued and terminates further transfer of data to the host. in addition, a receive message header, corresponding to the partially received message, indicates a long message error condition, and an interrupt de scriptor is generated toward the host indicating the same error condition. table 5-26. maximum message length register bit field name value description 31:14 rsvd 0 reserved. 13:0 rmaxfrm[13:0] ? defines a limit fo r the maximum number of bytes allowe d in a received hdlc message. valid values for the register range from 0 to 16 k ? 1. the formula to set maxfrm is: maxfrm = max allo wed message length (bytes) + fcs (bytes) ? 2. where: fcs = 0 for non-fcs mode fcs= 2 byte for hdlc-16 mode fcs = 4 byte for hdlc-32 mode. a too long message interrupt is generated when the number of bytes in the processed message exceeds max allowed message length. note(s): the host may change the value of maximum message length register only if the channel that uses its value (according to maxsel-bit in the configur ation memory) is inactive.
28560-DSH-001-B mindspeed technologies? 5 - 29 advance information cx28560 data sheet the cx28560 memory organization 5.7.4 rbuffc channel configuration register this register controls the operation mode for a channel. it contains parameters necessary for the division of the internal memory to channel fifos. there is one channel configuration register for each logical channel (i.e., 2047). the cx28560?s internal rx memory is a 320 kb dual ram, which may be split to 2047 parts, one part for each channel. the allocation granularity is 8 bytes. in the cx28560, regardless of its bit rate, each channel receives an identical allocation of memory. the differ ence in bit rates is accounted for by extra servicing of faster channels according to the flexiframe algorithm. hence the length of a channel?s buffer is set once (see table 5-30 ). however, for each active channel it is required to specify the start address of th e internal data buffer. (see appendix e: buffer controller fifo size calculation ) note: the host must set the buffers so there is no overlap between buffers belonging to different channels. each receive ch annel must be allocated buffer space before the channel can be activated. in addition the end address of each channel must be higher than the start address ? no roll-over at the end of the data fifo is permitted. table 5-27. rbuffc channel configuration register bit field name value description 31:22 rsvd 0 reserved. 21 reomien 0 end of message (without errors) interrupt disabled. 1 end of message (without e rrors) interrupt enabled. any error-free message received will cause this interrupt to be generated. 20 rerrien 0 end of errored message interrupt disabled. 1 end of errored message interrupt enabled. any message received containing any error (other than too short) will cause this interrupt to be generated. 19 rtooshien 0 end of message with t oo short error interrupt disabled. 1 end of message with too short error interrupt enabled. any message containing an error for which data has not been passed to the rbuffc will cause a too short error interrupt to be generated. 18 rcmdcien 0 end of channel comma nd execution interrupt disabled. 1 end of channel command execution interrupt enabled. on completion of command (activation or de activation) an interr upt will be generated. 17:16 rsvd 0 reserved. 15:0 rstartadd ? channel data fifo st art pointer?in units of qwords.
5-30 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.7.5 rbuffc flexiframe memory the rbuffc flexiframe memory provides the rbuffc with the order in which to service the channels ? a timing scheduler. the rbuffc runs through the flexiframe memory line by line, servicing the channel number as in the flexiframe memory. the flexiframe holds a maximum of 21504 entries and a minimum of 12. the number of entries contained in the flexiframe is stor ed in the flexiframe control register, and should be an exact multiple of 4. the value 0 in the ch annel number represents an empty cycle and will be treated as a nop by the rbuffc. because of the flexiframe memory organization in lines of four regist ers each, access to re gisters must be in multiples of four registers. 5.7.6 rbuffc flexifram e control register this register contains the characteristics of the flexiframe being programmed. when moving to a new flexiframe this register is vital for the smooth transition. in order to swap to a new flexiframe, the host sh ould write the new flexiframe to the table 5-28 , then write the flexiframe control register with the new frame size, the rnfframei interrupt enable set to 1 or 0, and the rnfframe field set to 1. the host knows that the transition to the new flexiframe ha s been made either when a nfframei interrupt is generated (if the rnfframei en was set to 1) or by polling the rnfframe bit for a 0 value. an additional change of flexiframe before some acknowledgement has been recorded may produce undefined behavior. table 5-28. rbuffc flexiframe memory bit field name value description 31:11 rsvd 0 reserved. 10:0 rchannel ? logical channel number assigned to slot in flexiframe. table 5-29. rbuffc flexiframe control register bit field name value description 31:26 rsvd 0 reserved. 25 rnfframeien 0 change of flexiframe complete interrupt disabled. 1 change of flexiframe co mplete interrupt enabled. once the rbuffc has completed the switch to the new flexiframe a change of flexiframe complete inte rrupt will be generated. 24 rnfframe ? new flexiframe indication. this bit serves as an indication to the rb uffc to switch to the new flexiframe. when the rbuffc completes the switch to the new flexiframe, it resets this indication to 0. it is illegal for the system to set this bit to 0 as this will produce undefined behavior. 23:15 rsvd 0 reserved. 14:0 rfframesize[14:0] rfframesize[1:0] ? 3 flexiframe size. this field provides the rbuffc the actual number of entries in the flexiframe minus one. because the number of entries in the flexiframe must be a multiple of four, the last two bits of th is field will be set to 11b. the value of this field may range from 11 to 21503 (indicating flexif rame sizes of 12 to 21504 respectively).
28560-DSH-001-B mindspeed technologies? 5 - 31 advance information cx28560 data sheet the cx28560 memory organization 5.7.7 rbuffc data fifo size register this register defines the size of each channel?s data fifo in 8-byte granularity. this size is fixed once for the receive direction since all the chan nels are allocated the same amount of buffer memory regardless of their bit rate. the size of th e buffer should be allocated as a multiple of 8, minimum 160 bytes per channe l and maximum 32 kb (see appendix e ). 5.7.8 rbuffc fragment size register this fixes the maximum number of words of payload (i.e., packet data, not fragment header) that will be transferred to the system over the pos-phy data interface in the interval fixed by table 5-32 . for the calculation to determine the relevant fragment size (see appendix e ). 5.7.9 rbuffc flexiframe slot time register number of cycles per slot ? determines the numb er of cycles per slot and as consequence the timing of the write transaction of a fragment towards the pos-phy. table 5-30. rbuffc data fifo size register bit field name value description 31:14 rsvd 0 reserved. 13:0 rdfifosize ? 0 data fifo size (per channel) in dwords. the value in this regist er applies to all the channels. the value in this field must be even. table 5-31. rbuffc fragment size register bit field name value description 31:8 rsvd 0 reserved. 7:0 rnumwordsfrag ? maximum number of words of data alloca ted to a fragment. the minimum programmable value is 8 dwords, and the ma ximum 64 dwords. the register is based on a one-based count. the length of the fragment is fixed once for the receive direction. table 5-32. rbuffc flexiframe slot time register bit field name value description 31:8 rsvd 0 reserved. 7:0 rnumcycleslot ? minimum number of cy cles allocated pe r flexiframe slot. this c ount is zero based, all values are supported. if this is larger than three plus the number of dwords ready to be sent to the system, a gap will be created betw een fragments. the aim of this is to allow the system to fix the amount of time it needs to perform regular (and irregular) activities. when configured to 0, the rbuffc will work ?as fast as possible??the minimum number of cycles possible (4) will be spent servicing empty slots.
5-32 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.7.10 rbuffc counter memory there are 2047 counters of each kind, one for each cha nnel. the counters for each channel can be read by giving the base ad dress of the channels counters and length long enough to encompass them all (counters can be read on a per channel basis or for all channels). for a full description of the counters and their use, see appendix a . table 5-33. rbuffc counter memory length counter name reset value description 24 roctetctr 0 octet counter. the number of data bytes/octets rece ived per channel. 24 rmsgctr 0 message counter. the number of non-erro red messages received per channel. 24 rmalignerrctr 0 message alignment error counter. the number of messages wi th message alignment errors received per channel. 24 rfcserrctr 0 fcs error counter. the number of messages with f cs errors received per channel. 24 rabrcerrcnt 0 abort condition error counter. the number of messages with abort c ondition errors rece ived per channel. 24 rlongmsgcnt 0 too long me ssage error counter. the number of messages with too long message errors rece ived per channel. 24 rtshortmsgcnt 0 too shor t message error counter. the number of messages with too short message errors received. to use this counter, the sht interrupt must be enabled (see table 5-25, rslp channel configuration register ).
28560-DSH-001-B mindspeed technologies? 5 - 33 advance information cx28560 data sheet the cx28560 memory organization 5.7.11 rsiu time slot configuration register 5.7.11.1 receive time slot map the receive time slot map comprises two 8192 entry memories containing slot to group/channel mapping, and two 512 entry memories of pointers per port or per group. one set of maps is provided per direction. each port is assigned a start and end address within the time slot/group map, and runs on the slots between these addresses. each slot may be either a direct mapping to a chan nel number and relevant parameters, or a pointer to a group. if the slot contains a pointer to a group, this implies ds0 extraction is to be performed. the relevant address within the group map pointers will be accessed to retrieve start, length and current pointer s, and the channel number and relevant parameters will be retrieved from the group map (see figure 5-2 ). note: the group map and ds0 bit extraction are only to be used in ports that are configured as tsbus mode in the table 5-39 ; for other ports, a time slot mapped with the ds0 extraction bit set causes undefined behavior and so is illegal. a channel may be mapped to more than one time slot within a port (hyper- channeling), but mapping of one channel to more than one port is illegal and will cause undefined ordering of data. henc e numerous mappings of time slots are possible, multiple time slot s can be mapped to a single channel or in the case of tsbus ds0 extraction mode mode, to a single group. for each serial port one time slot map is required (per direction), and when in tsbus ds0 extraction mode, group maps should be provided per direction. each map is configured independently. in the receive direction the registers described in table 5-34 , table 5-35 , table 5-36 and table 5-37 are used for configuration of the time slot map. figure 5-2. receive time slot map pointers 101302_012 startad length length ds0 # chan # group en m.e. 1st a b c ... d e 0 0 1 0 ... 0 0 x ... ??? ??? ??? ??? ??? ??? endaddr staddr # chan en m.e. 1st time slot pointers ts/group map group map pointers group map ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
5-34 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.7.11.2 rsiu time slot configuration descriptor for each time slot in the time slot map, there is an rsiu time slot configuration descriptor. there are 8192 entries in memory that set the translation between time slots and logical channels or groups for each of the cx28560's 32 ports. the actual mapping of these time slot descriptors to th e 32 ports is done by 32 sets of pointer pairs (receive and transmit), one pair set fo r each port, which indicates the start and the end address of the memory location that belongs to the configured port. time slot pointer allocation is described in rsiu time slot pointer allocation. the bit fields of rsiu time slot configuration descriptor include information:  this time slot should be referred to a group map for a higher level of extraction  time slot is enabled or disabled  time slot is a full ds0, or sub-channeling enabled so that only a part of 64 kbps transports information  indicates if it is the first time slot assigned to the logical channel  logical channel number (max 2047). table 5-34 specify the content of each receive ti me slot configuration descriptor. the type of entry in the specific row of the ts/group map is determined by the ds0 bit. table 5-34. rsiu ts/group map bit field name value description 31:18 rsvd 0 reserved 17 rds0 0 ds0 extraction mode is disabled 1 ds0 mode is enabled. this bit must only be set if the port to which this time slot is c onnected is configured as tsbus mode see ) 16:14 rsvd 0 reserved 13:3 rchannel[10:0] ? if ds0 extr action mode is disabled fo r this time slot, this field represents the logical channel number assigned to the time slot. rds0_group ? if ds0 extracti on mode is enabled for this time sl ot, the lower 9 bits of this field represent the logical group numbe r assigned to the time slot. 2 rts_enable 0 time slot disabled or ds0 extraction mode is enabled. 1 time slot enabled. this bit is only valid if ds0 extrac tion mode is disabled (rds0 = 0) 1 rmasken_sb 0 the rmask_sb bi t field () is ignored. all the 8 bits of the time slot are processed. this value is also possible if ds0 extraction mode is enabled. 1 allow data mask for time slot. only the bi ts specified by the rm ask_sb bit field () are processed. this bit is only valid if ds0 extr action mode is di sabled (rds0 = 0) 0 rfirst_ts 0 this bit field indicates that the specified time slot is not th e first time slot of the logical channel or that ds0 extraction mode is enabled. 1 this bit field indicates that the specified time slot is the first time slot of the logical channel. this bit is only valid if ds0 ex traction mode is disabled (rds0 = 0) note(s): if a serial port is confi gured to transparent mode, each channel defined to operate over the serial port mu st have one time slot assi gned to that logical channel as the first time slot for that channel.
28560-DSH-001-B mindspeed technologies? 5 - 35 advance information cx28560 data sheet the cx28560 memory organization when ds0 extraction mode is enabled, the receive group map for that group is referred to in order to attain relevant in formation regarding the channel number, slot enabled, mask enabled and first time slot bi ts. the format of an entry in the group is shown in table 5-35 . table 5-35. rsiu group map bit field name value description 31:14 rsvd 0 reserved. 13:3 rchannel[10:0] ? logical channel nu mber assigned to the time slot. 2 rts_enable 0 time slot disabled. 1 time slot enabled. 1 rmasken_sb 0 the rmask_sb bit field (rslp channel configurati on descriptor) is ignored. all the 8 bits of the time slot are processed. 1 allow data mask for the specified time sl ot. the bits specified by rmask_sb bit field (rslp channel configuration descriptor) are processed. 0 rfirst_ts 0 this bit field indicates that the specified time slot is not th e first time slot of the logical channel. 1 this bit field indicates that the specified time slot is the first time slot of the logical channel. note(s): if a serial port is configured to opera te in channelized mode, each channel defined to operate over the serial port must ha ve one time slot assi gned to that logical channel that is defined as the first time slot for that channel.
5-36 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.7.12 rsiu time slot po inter allocation register there is one rsiu time slot pointer allocation descriptor for each of the cx28560?s 32 serial ports. th is register sets the start and end time slot address for the specific configured port. the difference be tween the configured end and start address specifies the number of time slots al located for the specified serial port. 5.7.12.1 time slot allocation rules 1. when the serial port is configured to one of the conventional modes, and both pointers point to the same location, this port should be configured to operate in unchannelized mode. this is done by setting the rporttyp field in table 5-39 to 0. 2. when the serial port is configured to one of the conventional modes, if there are two or more time slots, the rporttyp field in rsiu port configuration register must be set to either 5 for no n-t1 framing, or 1 to enable t1 framing. 3. when the serial port is configured to tsbus mode, rsiu time slot pointer allocation descriptor is to be configured to support more than eight time slots and the rport_type bit fiel d in rsiu port configuration register must be set to tsbus mode. in the case of unchannelized mode (i .e., the rporttyp field in rsiu port configuration register is programmed to 0), the cx28560 assumes that only one entry (the one pointed to by startad) is us ed for this port. this frees the endad pointer to point to any location in the rsiu time slot memory. table 5-36 describes the bit fields in rsiu time slot pointer allocation descriptor. 5.7.13 rsiu group map po inter allocation register splits table 5-35 into group sections. table 5-36. rsiu time slot/group map pointer allocation register bit field name value description 31:29 rsvd 0 reserved. 28:16 rendad_ts[12:0] ? ending location in the receive time slot map of the last time slot assigned to this port. 15:13 rsvd 0 reserved. 12:0 rstartad_ts[12:0] ? starti ng location in the receive time slot ma p of the first time slot assigned to this port. table 5-37. rsiu group map pointer allocation register bit field name value description 31:19 rsvd 0 reserved 18:6 rstartad ? starting locati on in the ts map of the first group time slot. 5:0 rlength ? the number of time slots allo cated to the group (zero-based count).
28560-DSH-001-B mindspeed technologies? 5 - 37 advance information cx28560 data sheet the cx28560 memory organization 5.7.14 rsiu group state register this memory is used internally by the rs iu. the state field of groups belonging to one port must be set to zero (i.e., disable state) before the port is enabled. the relevant group register is found at an offset of the group number from the base address. there is one register per group. 5.7.15 rsiu port configuration register there is a receive port configuration regist er for each serial port. it defines how the cx28560 interprets and synchronizes the received bit streams associated with the serial port. table 5-39 describes the bit fields in rsiu port configuration register. table 5-38. rsiu group state register bit field name value description 31:2 rsvd 0 reserved 1:0 group_state 0 disable stat e, where group is disabled 1 enable state, where group is enabled 2 polling state ? polling handling 3rsvd table 5-39. rsiu port configuration register (1 of 2) bit field name value description 31:15 rsvd 0 reserved. 14 rgsync_edge 0 receive r gsync?falling edge 1 receiver gsync?rising edge 13 rxenbl 0 receive port disabled . logically resets the time slot , regardless of rts_enable bit field in rsiu time slot conf iguration descriptor. this does not affect the bit values in any time slot descriptor. 1 receive port enabled. this bi t field acts as a logical an d between rts_enable bit field in rsiu time slot configurat ion descriptor and time slot. logically, if rts_enable bit field in rsiu time slot configurat ion descriptor is enabled, it allows all channels with time sl ot enable bits set to start processing data. this does not affect the bit values in any time slot descriptor. 12 rsvd 0 reserved.
5-38 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 11:9 rport_type [2:0] 0 unchannelized mode. it is the user?s responsibilit y to configure the time slot map to contain one time slot. 1 t1 mode. this mode implies 24 time slots and t1 sign aling. it is the user?s responsibility to configure the time slot map to contain exactly 24 time slots. 2 nx64 mode = 2 time slots it is the user?s responsibility to configure the time slot ma p to contain exactly two time slots. 3 nx64 mode = 3 time slots it is the user?s responsibility to configure the time slot map to contain exactly three time slots. 4 nx64 mode = 4 time slots it is the user?s responsibility to configure the time slot map to contain exactly four time slots. 5 nx64 mode it is the user?s responsibility to configure the time slot ma p to contain more than four time slots. 6 tsbus mode it is the user?s responsibility to configure the time slot map to contai n at least eight time slots. for the first twelve ports this mode ca n also be used for ds0 extraction. this is performed by the use of the ds0 bit in the time slot/group map. this mode is considered to be ds 0 extraction mode. 7 reserved 8:6 rsvd 0 reserved 5 rsync_edge/ rstuff_ edge 0 receiver frame synchronization/rec eive stuff indica tion?falling edge. rsync/rstuff input sampled in on falling edge of rclk. 1 receiver frame synchronization/rec eive stuff indica tion?rising edge. 4 rdat_edge 0 receiver data ? falling edge. rdat input sampled in on falling edge of rclk. 1 receiver data ? rising edge. 3 roof_edge/ rtstb_edge 0 receiver out of frame/ts bus strobe?falling edge. roof/ tstb input sampled in on falling edge of rclk. 1 receiver out of frame?rising edge. 2 roofabt 0 oof message processing enabled. wh en oof condition is detected, continue processing incoming data. siu sh ould not report about the oof. 1 oof message processing disabled. 1 roofien 0 out of frame/frame recovery interrupt/ general int disabled 1 out of frame/frame recovery/general interrupt enabled. 0 rcofaien 0 change of frame alignment interrupt disabled. 1 change of frame alignment interrupt enabled. if cofa is detected, genera te interrupt indicating cofa. table 5-39. rsiu port configuration register (2 of 2) bit field name value description
28560-DSH-001-B mindspeed technologies? 5 - 39 advance information cx28560 data sheet the cx28560 memory organization 5.8 transmit path registers transmit path registers contain the information nece ssary to configure the receive direction. this configuration includes registers that are related to the buffc block, host interface, registers that control the tslp, and tsiu. 5.8.1 tslp channel status register the tslp channel status register is a read only (ro) register. it provid es information from tslp block regarding the channel state. there is one tslp channel status register for each of the cx28560?s channels (i.e., 2047 registers). table 5-40. tslp channel status register bit field name host default value value description 31:4 rsvd r x 0 reserved. 3:1 rsvd r x 0 reserved. 0 tactive r x 0 1 channel inactive. the channel has been deactivated due to either a service request channel deactivation, reset (pci reset or soft chip reset), or one of the following tr ansmit errors: txbuff, txcofa. channel active. the channel has been activate d by service request channel activation.
5-40 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.8.2 tslp channel configuration register the transmit channel configuration register contains configuration bits applying to the logical channels w ithin the cx28560. there are 2047 such registers, one for each channel. the tslp channel co nfiguration register configur es aspects of the channel common to all messages passing through the channel. one descriptor exists for each logical channel direction. table 5-41 lists the values and desc riptions of each channel configuration descriptor. for each channel to be used in the cx28560, this register must be configured before activa tion (no default values exist). table 5-41. tslp channel configuration register bit field name value description 31:30 tprotcol[1:0] 0 transparent. 1 hdlc with no fcs. used in tslp for full packet forwarding and/or channel moni toring application. 2 hdlc with fcs16 (fcs? 2 bytes). 3 hdlc with fcs32 (fcs? 4 bytes). 29 tinv 0 data inversion disabled. 1 data inversion enabled. message is transferred to the siu with polarity change (the inversion is done to all bits passed). 28:21 tmask_sb[7:0] ? data mask. actual data is only transmit ted on bits with a value of 1 (e.g., mask = 10000001, then only bits 0 and 7 contain ch annel's data). the other bi ts are padded with non-data. enables the sub-channeling feature. note 0h is an invalid value. 20:3 rsvd 0 reserved. 2 tpadj 0 pad count adjustment disabled 1 pad count adjustment enabled. the tslp counts the num ber of zero insertions perfor med in a message, and reduces the number of inter-message idle codes tran smitted accordingly. the reduction of the number of idle code bytes is calculated by dividi ng the number of zero insertions by 8 and rounding down. this feature allows the hos t approximate control over the bit rate on the line. 1 tbuffien 0 underrun interrupt disabled. 1 underrun interrupt enabled. 0 teomien 0 transmit eom interrupt disabled. 1 transmit eom interrupt enabled. an interrupt is generated when an end of message is transm itted by the cx28560.
28560-DSH-001-B mindspeed technologies? 5 - 41 advance information cx28560 data sheet the cx28560 memory organization 5.8.3 tbuffc channel configuration register this register controls the operation mode for a channel. it contains parameters necessary for the division of the internal memory to channel fifos. there is one channel configuration register for each logical channel (i.e., 2047). the cx28560?s internal tx memory is a 384 kb dual ram, which may be split to 2047 parts, one part for each channel. the allocation granul arity is one dword (4 bytes). in the cx28560, regardless of its bit rate, each channel receives an identical allocation of memory. the differ ence in bit rates is accounted for by extra servicing of faster channels according to the flexiframe algorithm. hence the length of a channel?s buffer is set once (see table 5-45 ). however, for each active channel it is required to specify the start address of the internal data buffer. since this register is wider than 32 bits, it spreads over 2 consecu tive addresses. when writing to this register, the first 32 least si gnificant bits are written to the first address and the upper bits are written to the lowest possible bits in the second address. note: the host must set the buffers so there is no overlap between buffers belonging to different channels. each receive ch annel must be allocated buffer space before the channel can be activated. table 5-42. tbuffc channel configuration register len field name value description 33 tcmdcien 0 end of channel comma nd execution interrupt disabled. 1 end of channel command execution interrupt enabled. on completion of command (activation or de activation) an interr upt will be generated. 32 tbovflwien 0 tbuffc ch annel buffer overflow interrupt disabled. 1 tbuffc channel buffer ov erflow interrupt enabled. 31:30 tprotocol 0 fcs protocol. this should be th e same as the corresponding tslp configuration. transparent 1 hdlc with no fcs 2 hdlc with 16 bit fcs 3 hdlc with 32 bit fcs 29:13 tstartadd ? channel data fifo start pointer?0 based. the addresses are allocated in dword (4-byte) granularity. 12:0 tthreshold ? channel buffer threshold level. the cx28560 will not start to transmit a new message until threshold number of dwords (4 bytes) are stored in the channels internal buffer. if the message to be transmitted is less than the threshold, th e cx28560 will start to transmit the message when the end of message is detected (threshold is a zero based count).
5-42 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.8.4 tbuffc flexiframe memory the tbuffc flexiframe memory provides the tbuffc with the order in which to service the channels ? a timing scheduler. on ce a channel is chosen by the flexiframe algorithm, if necessary a transmission repo rt is sent to the host over the flow conductor pos-phy interface. the tbuffc runs through the flexiframe memory line by line, servicing the channel numb er as in the flexiframe memory. the flexiframe holds a maximum of 21504 entries and a minimum of 12. the number of entries contained in the flexiframe is stor ed in the flexiframe control register, and should be an exact multiple of 4. the value 0 in the ch annel number represents an empty cycle and will be treated as a nop by the tbuffc. because of the flexiframe memory organizat ion in lines of four registers each, access to registers must be in mu ltiples of four registers. table 5-43. tbuffc flexiframe memory bit field name value description 31:11 rsvd 0 reserved. 10:0 tchannel ? logical channel number assigned to slot in flexiframe.
28560-DSH-001-B mindspeed technologies? 5 - 43 advance information cx28560 data sheet the cx28560 memory organization 5.8.5 tbuffc flexiframe control register this register contains the characteristics of the flexiframe being programmed. when moving to a new flexiframe this register is vital for the smooth transition. in order to swap to a new flexiframe, the host sh ould write the new flexiframe to the table 5-43 , then write the flexiframe control register with the new frame size, the tnfframei interrupt enable set to 1 or 0, and the tnff rame field set to 1. the host knows that the transition to the new flexiframe ha s been made either when a tnfframei interrupt is generated (if the tnfframe ien was set to 1) or by polling the tnfframe bit for a 0 value. an addition al change of flexiframe before some acknowledgement has been recorded may produce undefined behavior. table 5-44. tbuffc flexiframe control register bit field name value description 31:26 rsvd 0 reserved. 25 tnfframeien 0 new flexifra me interrupt disabled. 1 new flexiframe interrupt enabled. once the tbuffc has completed the switch to the new flexiframe a new flexiframe interrupt will be generated. 24 tnfframe ? new flex iframe indication. this bit serves as an indication to the tbuffc to switch to the new flexiframe. when the tbuffc completes the switch to the new flexiframe, it resets this indication to 0. it is illegal for the system to set this bit to 0 as this will produce undefined behavior. 23:15 rsvd 0 reserved. 14:2 1:0 tfframesize[14:2] tfframesize[1:0] ? 3 flexiframe size. this field provides the rbuffc the actual number of entries in the flexiframe minus one. since the number of entries in the flexif rame must be a multip le of four, the last two bits of this fiel d will be set to 11b. the value of this field may range from 11 to 21503 (indicating flexiframe si zes of 12 to 21504 respectively).
5-44 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.8.6 tbuffc data fifo size register this register defines the size of each channe l?s data fifo in dwords (4 bytes). this size is fixed once for the transmit directi on since all the channels are allocated the same amount of buffer memory regardless of their bit rate. th e size of the buffer should be allocated as a multiple of 4, minimum 80 bytes per channel and maximum 32 kb (see appendix e ). 5.8.7 tbuffc flexiframe slot time register number of cycles per slot ? a number in clock cycles that indicates the minimum slot time. per slot time, one fragment is receiv ed and one transmission report. range from 6?255 clock cycles. table 5-45. tbuffc data fifo size register bit field name value description 31:13 rsvd 0 reserved. 12:0 tdfifosize ? size of data fifo per channel in dwords. the value in this register applies to all channels. table 5-46. tbuffc flexiframe slot time register bit field name value description 31:8 rsvd 0 reserved. 7:0 tnumcycleslot ? minimum number of cy cles allocated per flexiframe slot. this count is zero based, and has a minimum of 0 and a maximum of 255. if this is larger than three plus the number of dwords ready to be sent to the system, a gap will be created between fragments. the aim of this is to allow the system to fix the amount of time it needs to perform regu lar (and irregula r activities). when configured to 0, the tbuffc will work in ?fastest possible? mode, i.e., each slot will take a minimum of 6 cycles.
28560-DSH-001-B mindspeed technologies? 5 - 45 advance information cx28560 data sheet the cx28560 memory organization 5.8.8 tbuffc counter memory there are 2047 counters of each kind, one for each channel. each is at an offset of it?s channels number from the base address. the counters for each chan nel can be read by giving the base address of the channels counters and length long enough to encompass them all. for a full description of the counters and their use, see appendix a . 5.8.9 tsiu time slot configuration register 5.8.9.1 transmit time slot map the transmit time slot map comprises two 8192 entry memories containing slot to group/channel mapping, and two 512 entry memo ries of pointers per port or per group. one set of maps is provided per direction. each port is assigned a start and end address within the time slot/group map, and runs on the slots between these addresses. each slot may be either a direct mapping to a ch annel number and relevant parameters, or a pointer to a group. if the slot contains a poi nter to a group, this implies ds0 extraction is to be performed. the relevant address within the group map pointers will be accessed to retrieve start, length and current pointers, and the channel number and relevant parameters will be retrieved from the group map (see figure 5-3 ). note: the group map and ds0 bit extraction are only to be used in ports that are configured as tsbus mode in table 5-53 ; for other ports, a time slot mapped with the ds0 extraction bit set causes undefined behavior and so is illegal. a channel may be mapped to more than one ti me slot within a port (hyperchanneling), but mapping of one channel to more than one port is illegal and will cause undefined ordering of data. hence numerous mappings of time slots are possible, multiple time slots can be mapped to a single channel or in the case of ds0 extraction mode, to a single group. for each serial port one time sl ot map is required (per direction), and when in tsbus ds0 extraction mode, group maps should be provid ed per direction. each map is confi gured independently. table 5-47. tbuffc counter memory length counter name reset value description 24 tmsgctr 0 message counter. the number of messages transmitted per channel 24 toctetctr 0 octet counter. the number of da ta octets transm itted per channel 24 tabrtmsg 0 aborted message counter. the number of messages with mess age aborted during their transmission.
5-46 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet in the transmit direction the registers described in table 5-48 , table 5-49 , table 5-50 , and table 5-51 are used for configuration of the time slot map. figure 5-3. transmit time slot map pointers 101302_012 startad length length ds0 # chan # group en m.e. 1st a b c ... d e 0 0 1 0 ... 0 0 x ... ??? ??? ??? ??? ??? ??? endaddr staddr # chan en m.e. 1st time slot pointers ts/group map group map pointers group map ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
28560-DSH-001-B mindspeed technologies? 5 - 47 advance information cx28560 data sheet the cx28560 memory organization 5.8.9.2 tsiu time slot configuration descriptor for each time slot in the time slot map, there is a tsiu time slot configuration descriptor. there are 8192 entries in memory that set the translation between time slots and logical channels or groups for each of the cx28560's 32 ports. the actual mapping of these time slot descriptors to th e 32 ports is done by 32 sets of pointer pairs (receive and transmit), one pair set fo r each port, which indicates the start and the end address of the memory location that belongs to the configured port. time slot pointer allocation is described in tsiu time slot pointer allocation. the bit fields of tsiu time slot configuration descriptor include information:  this time slot should be referred to a group map for a higher level of extraction  time slot is enabled or disabled  time slot is a full ds0, or sub-channeling enabled so that only a part of 64 kbps transports information  indicates if it is the first time slot assigned to the logical channel  logical channel number (max 2047). table 5-48 specifies the content of each receive time slot configura tion descriptor. the type of entry in the specific row of the ts/group map is determined by the ds0 bit. table 5-48. tsiu ts/group map bit field name value description 31:18 rsvd 0 reserved 17 tds0 0 ds0 extraction mode is disabled 1 ds0 mode is enabled. this bit must only be set if the port to which this time slot is connected is configured as tsbus mode see ) 16:14 rsvd 0 reserved 13:3 tchannel[10:0] ? if ds0 extraction m ode is disabled for this time slot , this field represents the logical channel number assigned to the time slot. tds0_group ? if ds0 extraction mode is enabled for this time slot, the lower 9 bits of this field represent the logical channel number assigned to the time slot. 2 tts_enable 0 time slot disabled or ds0 extraction mode is enabled. 1 time slot enabled. this bit is only valid if ds0 extrac tion mode is disabled (tds0 = 0) 1 tmasken_sb 0 the tmask_sb bit field () is ignored. all the 8 bits of th e time slot are processed. this value is also possible if ds 0 extraction mode is enabled. 1 allow data mask for time slot. only the bits specified by the tmask_sb bit field () are processed. this bit is only valid if ds0 extraction mode is disabled (tds0 = 0) 0 tlast_ts 0 this bit field indicates that the specified time slot is not th e last time slot of the logical channel or that ds0 extraction mode is disabled (tds0 = 0) 1 this bit field indicates that the specified time slot is the last time slot of the logical channel note(s): if a serial port is configured to tran sparent mode, each channel defined to operate over the serial port must have one time slot assigned to that logical channel as the last time slot for that channel.
5-48 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet when ds0 extraction mode is enabled, the receive group map for that group is referred to in order to attain relevant in formation regarding the channel number, slot enabled, mask enabled and first time slot bi ts. the format of an entry in the group is shown in table 5-49 . table 5-49. tsiu group map bit field name value description 31:13 rsvd 0 reserved. 13:3 tchannel[10:0] ? logical channel num ber assigned to the time slot. 2 tts_enable 0 time slot disabled. 1 time slot enabled. 1 tmasken_sb 0 the tmask_sb bit field (tslp channel configuration descriptor) is ignored. all the 8 bits of the time slot are processed. 1 allow data mask for the specified time slot . the bits specified by tmask_sb bit field (tslp channel configuration descriptor) ar e processed. 0 tlast_ts 0 this bit field indicates that the specified time slot is not th e last time slot of the logical channel. 1 this bit field indicates that the specified time slot is the last time slot of the logical channel. note(s): if a serial port is configured to opera te in channelized mode, each channel defined to operate over the se rial port must have one time slot assigned to that logical channel that is defined as the first time slot for that channel.
28560-DSH-001-B mindspeed technologies? 5 - 49 advance information cx28560 data sheet the cx28560 memory organization 5.8.10 tsiu time slot pointer allocation register there is one tsiu time slot pointer allocation descriptor for each of the cx28560?s 32 serial ports. th is register sets the start and end time slot address for the specific configured port. the difference be tween the configured end and start address specifies the number of time slots al located for the specified serial port. 5.8.10.1 time slot allocation rules 1. if both pointers point to th e same location, this port should be configured to operate in unchannelized mode. this is done by setting the tporttyp field in table 5-53 to 0. 2. if there are two, three, or four time sl ots, the tporttyp field in tsiu port configuration register must be set to 2, 3, or 4 respectively. 3. if there are more than four time slot s, the tporttyp field in tsiu port configuration register must be set to either 5, if it is no t t1 framing, or 1 if it is. 4. if serial port is configured to ts bus mode, tsiu time slot pointer allocation descriptor is configured to support more than eight time slots and the tport_type bit field in tsiu port configuration register must be set to tsbus mode. in the case of unchannelized mode (i .e., the tporttyp field in tsiu port configuration register is programmed to 0), the cx28560 assumes that only one entry (the one pointed to by tstartad) is us ed for this port. this frees the tendad pointer to point to any location in the tsiu time slot memory. table 5-36 describes the bit fields in tsiu time slot pointer allocation descriptor. table 5-50. tsiu time slot/group map pointer allocation register bit field name value description 31:29 rsvd 0 reserved. 28:16 tendad_ts[12:0] ? ending location in the receive time slot ma p of the last time slot assigned to this port. 15:13 rsvd 0 reserved. 12:0 tstartad_ts[12:0] ? starting locati on in the receive time slot map of the first time slot assigned to this port.
5-50 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.8.11 tsiu group time sl ot map pointers register splits table 5-49 into group sections. 5.8.12 tsiu group state register this memory is used internally by the tsiu. before a port is enabled, the state field of groups to be enabled must be set to zero before the port is enabled. the relevant group register is found at an offset of the group number from the base address. this is typically done on reset of the chip, or immediately after a port is disabled. there is one register per group. table 5-51. tsiu group map pointers register bit field name value description 31:19 rsvd 0 reserved 18:6 tstartad ? starting location in the ts map of the first group time slot 5:0 tlength ? number of time slots allo cated to the group (zero based count) table 5-52. tsiu group state register bit field name value description 31:2 rsvd 0 reserved 1:0 group_state 0 disable stat e, where group is disabled 1 enable state, where group is enabled 2 polling state?polling handling 3rsvd
28560-DSH-001-B mindspeed technologies? 5 - 51 advance information cx28560 data sheet the cx28560 memory organization 5.8.13 tsiu port c onfiguration register there is a transmit port configuration register for each serial port. it defines how the cx28560 interprets and synchronizes the received bit streams associated with the serial port. table 5-53 describes the bit fields in tsiu port configuration register. table 5-53. tsiu port configuration register (1 of 2) bit field name value description 31:15 rsvd 0 reserved. 14 tgsync__edge 0 transmitt er gsync?falling edge 1 transmitter gsync?rising edge 13 txenbl 0 transmit port disabled. logically resets the time slot, regardless of tts_enable bit field in tsiu time slot configuration descriptor. this does not affect th e bit values in any ti me slot descriptor. 1 transmit port enabled. this bit field acts as a logical and betw een tts_enable bit field in tsiu time slot configuration descript or and time slot. logically, if tts_enable bit field in tsiu time slot configuration desc riptor is enabled, it allows all channels with time slot enable bits set to start proc essing data. this does not affect the bit values in any time slot descriptor. 12 rsvd 0 reserved. 11:9 tport_type [2:0] 0 unchannelized mode. it is the user?s responsibility to configure the time slot map to contain one time slot. 1 t1 mode. this mode implies 24 time slots and t1 signaling. it is the user?s responsibility to configure the time slot map to contain exactly 24 time slots. 2 nx64 mode = 2 time slots it is the user?s responsibility to configure the time slot map to contain exactly two time slots. 3 nx64 mode = 3 time slots it is the user?s responsibility to configure th e time slot map to contain exactly three time slots. 4 nx64 mode = 4 time slots it is the user?s responsibility to configure th e time slot map to cont ain exactly four time slots. 5 nx64 mode it is the user?s responsibility to configure the time slot map to contain more than four time slots. 6 tsbus mode. it is the user?s responsibility to configure th e time slot map to cont ain at least eight time slots. for the first twelve ports this mode can also be used for ds0 extraction. this is performed by the use of the ds0 bit in the time slot/group map. this mode is considered to be ds0 extraction mode. 7 reserved 8:6 rsvd ? reserved
5-52 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5 tsync_edge/ tstuff_ edge 0 transmitter frame synchr onization/transmitter stuf f indication?falling edge. tsync/tstuff input sampled in on falling edge of tclk. 1 transmitter frame synchr onization/transmitter stu ff indication?rising edge. 4 tdat_edge 0 transmitt er data?falling edge. tdat output will be sample d on falling edge of tclk. 1 transmitter da ta?rising edge. 3 tcts_edge/ ttstb_edge 0 transmitter clear to se nd/tsbus strobe ?falling edge. tcts/tstb input sampled in on falling edge of tclk. 1 transmitter clear to se nd/tsbus strobe ?rising edge. 2 tctsenb 0 clear to send disabled. 1 clear to send enabled. 1 tritx 0 transmit three -state disabled. when a port is enabled, but a time slot with in the port is not mapped via the time slot map, the transmitter outputs l ogic 1 on the output data signal 1 transmit three-s tate enabled. when a port is enabled, but a time slot with in the port is not mapped via the time slot map, the transmitter three-st ates the output data signal. 0 tcofaien 0 change of frame al ignment interrupt disabled. 1 change of frame alignm ent interrupt enabled. if cofa is detected, genera te interrupt indicating cofa. table 5-53. tsiu port configuration register (2 of 2) bit field name value description
28560-DSH-001-B mindspeed technologies? 5 - 53 advance information cx28560 data sheet the cx28560 memory organization 5.9 pos-phy transaction headers and packets 5.9.1 receive pos-phy data bus data is accumulated in channe l buffers in the cx28560 until either an end of message is detected, or enough data has been collated to form a fragment (as configured by the user). once one of these conditions has been met, a fragment header is prep ared, and the data is sent (preceded by the header) to the system over a 32 b it pos-phy bus. all fragments sent to the system will be of equal length (as configured) except for the last fragment which contains only the last bytes of the message and may contain as little as 0 bytes of actual data. table 5-54. cx28560 receive header format bit field name value description 31:27 rsvd 0 reserved. 26:16 channel ? logical channel number. 15:12 msg status 0 message error encoding. 0 no error occurs. 1overflow. an internal buffer overflow occurred while the message was being received. 2 change of frame alignment (cofa) a cofa condition was detected whil e the message was being received. 3 out of frame (oof) a oof condition was detected while the message was being received. 4 abort condition an abort pattern (at least seven consecutive ones) was detected at the end of the message. 5 too long message the message received length reached the maximum set by the relevant maximum length register. 6 message alignment error the number of bits received in the message was not a multiple of 8 ? i.e., the message was not byte aligned. 7 fcs error the calculated fcs did not match that which was received with the message. 11 sop 0 this fragment is not the first fragment of a packet. 1 this fragment is the first fragment of a packet. 10 eop 0 this fragment is not the last fragment of a packet. the status bits are not valid. 1 this fragment is the last fragment of a packet. the status bits are valid. 9:0 length ? payload length. the number of bytes of data that follow the fr agment header. when th e eop bit is not set this will always be the maximu m length of a fragment. when th e eop bit is set, this field should be consulted to determ ine the number of da ta bytes contained in the fragment.
5-54 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet 5.9.2 transmit pos-phy data bus the system provides data to the cx28560 over a 32 bit pos-phy bus. when and how much data is to be provided to the cx28 560 can be calculated using the information received by the system over the flow conductor bus. all fragments sent to the cx28560 by the system should be of equal length (as configured) except for the last fragment which contains only the last bytes of the message and, therefore, may contain as little as 0 bytes of actual data. table 5-55. cx28560 transmit data header format bit field name value description 31:27 rsvd 0 reserved. 26:16 channel ? logical channel number. 15 comvalid command valid bit this bit is set on the last fragment of a packet to indicate that the idle code and pad count fields are valid. 0 command bits not valid. 1 command bits valid. 14:12 ic 0 inter-message idle code encoding. 0 hdlc ? flags (0x7e) transparent ? all ones (0xff) 1 hdlc ? all ones (0xff) transparent ? flags (0x7e) 2 all zeros (0x00) 3 reserved. 11:4 padcnt ? the minimum number of inter-mess age idle code bytes to be transmitted. hdlc: padcnt indicates the minimum number of idle codes to be inserted between the closing flags and the next opening flag (0x7e). padcnt = 0, yields a shared flag between two successive messages. padcnt = 1, yields the bit pattern: <0x7e><0x7e> padcnt = 2, yields the bit pattern: <0x7e><0x7e> transparent: indicates the (min imum number + 1) of idle codes to be inserted between successive messages. padcnt = 0, one idle code byte w ill be transmitte d between messages padcnt = 1, two idle code bytes will be transmitted between messages ====== note(s): there is no indication if more than pad cnt number of idle codes are inserted. 3 abort 0 no abort finish the message in an orderly manner ? ? 1 abort signal abort the present message by a dding at least 7 ones. continue with next message as usual (i.e., no de activation). 2:0 rsvd ? reserved.
28560-DSH-001-B mindspeed technologies? 5 - 55 advance information cx28560 data sheet the cx28560 memory organization 5.9.3 transmit flow conductor bus the cx28560 sends transmission reports to the system of the number of dwords (4 bytes) freed since the previous report. the reports are sent in the form of packets over an 8-bit, 100 mhz pos-phy bus. the requests packet s contain two fields?the channel number and the number of dwords freed. from this information the system can maintain an array of counters that count the amount of space presently available in each of the cx28560?s channels buffers. table 5-56. cx28560 flow conductor packet format bit field name value description 31:27 rsvd 0 reserved. 26:16 channel ? logical channel number 15:0 wsent ? number of dwords freed up for this spec ific channel since the pr evious report was sent over the flow conductor bus.
5-56 mindspeed technologies? 28560-DSH-001-B advance information the cx28560 memory organization cx28560 data sheet
28560-DSH-001-B mindspeed technologies? 6 - 1 advance information 6.0 functional description 6.1 initialization 6.1.1 reset there are two levels of reset: 1. hard pci reset 2. soft chip reset there are two ways to assert a reset: 1. assert the pci reset signal pin, prst*. 2. assert a service request through the host interface to perform the soft chip reset. after reset, the host must configure the cx285 60 for it to operate. this configuration includes several stages that should be performed in the following order: 1. pci configuration?must be performed only after hard pci reset 2. interrupt queue configuration 3. global configuration 4. pos-phy configuration 5. channels and ports configuration note: the interrupt queue must be configured before other registers. if the interrupt queue is not configured with the corr ect value of shared memory interrupt queue pointer and interrupt queue length, it may result in writes to location 0, because the service request acknowledge (sack) is written to a zero address location.
6-2 mindspeed technologies? 28560-DSH-001-B advance information functional description cx28560 data sheet 6.1.1.1 hard pci reset the pci reset is the most thorough level of reset in the cx28560. all subsystems enter into their initial states. pci reset is accomplished by asserting the pci signal, prst*. the prst* signal is an asynchronous signal on the pci bus. the reset signal can be activated in several ways. the system must always assert the reset signal on power- up. also, a host bus to pci bus bridging device should provide a way for software to assert the reset signal . additionally, software-controlle d circuitry can be included in the system design to specifically a ssert the reset signal on demand. asserting prst* towards the cx28560 guarantees that data transfer operations and pci device operations does not commence un til after the cx28560 has been properly initialized for operation. up on entering pci reset state, the cx28560 outputs a three- stated signal on all output pins and halts activity on all subsystems including the host interface, serial interface, and expansion bu s. the effects of a pci reset signal within the cx28560 takes ten pci clock cycles to complete. after this time, the host may communicate with the cx28560 using the pci configuration cycles. after the pci configuration, the device is not ready to start communication with the host via the service request mechanism until the srq_len bit field in service request register is set to zero. 6.1.1.2 soft chip reset a soft chip reset is a device-wide reset wi thout the host interface?s pci state being reset. serial interface operations and ebus operations are halted. the soft chip reset state is entered in one of two ways: 1. as a result of the pci reset 2. as a result of a soft chip reset host service request a soft chip reset causes the following:  transmit data signals, tdat, to be three-stated  ebus address-data lines to be three-stated and read enable and write enable outputs to be deasserted, haltin g all memory operations on ebus  all active channels to enter the channel deactivated state  buffer controllers to be reset, halting all pos-phy transactions  all the bits in the interrup t status register to clear  srq_len and bits in global configuration descriptor to clear the host acts as if this was a pci reset, except that the pci configuration does not need to be repeated (is kept unchanged). the host can assume that the reset was completed by the cx28560 and can start configuration of registers when the field srq_len is zero.
28560-DSH-001-B mindspeed technologies? 6 - 3 advance information cx28560 data sheet functional description 6.1.2 configuration a sequence of hierarchical initialization must occur after resets. the levels of hierarchy are as follows:  pci configuration?only after hardware reset  interrupt queue configuration  global configuration  pos-phy configuration  channel and port configuration channel and port configuration involves programming many registers and must be done to comply with its own hierarchy, as explained below. 6.1.2.1 pci configuration after power-up or a pci reset sequence, th e cx28560 enters a holding pattern. it waits for pci configuration cycles directed specifically for the cx28560. they are actually directed at the pci bus an d pci slot where the cx28560 resides. pci configuration involves pci read and write cycles. these cycles are initiated by the host and performed by a host-bus-to-pci-bus bridge device. the cycles are executed at the hardware signal level by the bridge device. the bridge device polls all possible slots on the bus it controls for a pci device, and then iteratively reads the configuration space for all su pported functions on each device. all information from the basic configuration sequence is forwar ded to the system controller or host processor controlling the bridge device. during pci configuration, the host can perform the following configuration for the cx28560:  read pci configuration space (device id entification, vendor identification, class code, and revision identification)  allocate 1 mb system memory range an d assign the base address register using this memory range  allow fast back-to-back transactions  enable pci system erro r signal line, serr*  allow response for pci parity error detection  allow pci bus-master mode  allow pci bus-slave mode  assign latency  assign interrupt line routing 6.1.2.2 service request mechanism after pci configuration is complete, a set of hierarchical configuration sequences must be executed to begin operation at the channel level. the service request mechanism is the main comm unication channel between the cx28560 and the host. it is used to configure the cx28560?s registers, read status registers, execute transactions over the ebus, and activate ports and channels. the mechanism is fully described in section 5.2.1 .
6-4 mindspeed technologies? 28560-DSH-001-B advance information functional description cx28560 data sheet 6.1.2.3 global configuration global configuration is initiated by th e host issuing service requests. global configuration specifies inform ation used across the entire device including all ports, all channels, and the ebus. for more information, refer to:  table 5-19, global configuration register .  table 5-20, ebus configuration register . note: device identification at the pci configur ation level must be used to identify the number of supported ports and channels in the cx28560, which in turn will affect the cx28560?s configuration. 6.1.2.4 interrupt queue configuration part of global configuration involves interrupt queue configuration. for more information, refer to chapter 5.0 , interrupt queue descriptor. 6.1.2.5 pos-phy configuration after global configuration has been comp leted, and the pci bus set up, pos-phy configuration should be performed by the host issuing service requests. for more information, see the following registers in chapter 5.0 :  receive pos phy control register  transmit pos phy control register  transmit threshold register 6.1.2.6 chip-level configuration there a several registers that require config uration once per chip. they are configured by the host issuing service requests. for further information, see chapter 5.0 , the following registers:  receive buffc data fifo size register  receive buffc flexi frame control register  receive buffc fragment size register  receive buffc flexiframe slot time register  receive slp maximum message length register (x3)  transmit buffc data fifo size register  transmit buffc flexi frame control register  transmit buffc flexiframe slot time register
28560-DSH-001-B mindspeed technologies? 6 - 5 advance information cx28560 data sheet functional description 6.1.2.7 channel and port configuration after general configuration, a specific ch annel and port configuration must be performed for each supported channel and port.  receive buffc flexiframe memory  transmit buffc flexiframe memory  receive buffc channel configuration register  receive slp channel configuration register  receive siu time slot/group map  receive siu group map  receive siu group state register  receive siu time slot/group map pointer allocation register  receive siu port configuration register  transmit buffc channel configuration register  transmit slp channel configuration register  transmit siu time slot/group map  transmit siu group map  transmit siu group state register  transmit siu time slot/group map pointer allocation register  transmit siu port configuration register channel operations serv ice request commands are:  ch_act: channel activate  ch_deact: channel deactivate 6.1.2.8 typical ini tialization procedure this section depicts a typi cal initialization procedure. 1. pci reset or soft chip reset (a soft chip reset is performed by a direct write to the cx28560 register map? in the soft chip reset register) note: after performing a soft chip reset, it is not necessary to reconfigure the pci. 2. pci configuration. 3. allocate areas in the shared memory for: a. interrupt queue b. service request table c. the cx28560?s configuration regist ers (global and lo cal per channel/ port/ts basis). 4. loop and wait for the service request length register to be ready. this step confirms that the cx28560 co mpleted its internal initialization. a. read the srq_len through the pci slave access and check if it is 0. b. if true, go to the next step. c. otherwise continue to check. 5. initialize the interrupt queue pointer re gister and interrupt length register by performing a direct write to the cx28560 registers with the address of the interrupt queue located in th e shared memory and its length. 6. check the port alive availability (i.e., txportalive and rxportalive) register by performing direct reads. for each active port the correspondent bit in txportalive and rxportalive registers must be set to 1. a. while port not alive (this is equiva lent with the correspondent bit not set) wait 8?16 serial clocks. b. if port not alive, poll until port alive. c. otherwise go to the next step.
6-6 mindspeed technologies? 28560-DSH-001-B advance information functional description cx28560 data sheet note: if the port is not alive in 16 system cl ocks then there are no serial clocks applied specific port. 7. initialize the service request pointer (srp) and service request length (srl) registers by performing a direct write to the cx28560 service request pointer and service request length register and update the value with the address all the srp table and its length in shared memory. 8. perform a config_wr service request an d wait for the sack or eoc (end of command) indication which copies the content of the register in shared memory to the relevant cx28560 internal register. the host can perform one config_wr service request given that all the register have been initialized in the shared memory pr ior to the config_wr service request, or can perform config_wr service request for each register individually. configuration write request procedure a detailed typical configuratio n write request procedure is 1. allocate the service request table in the shared memory. note: this allocation can be done in the very beginning (see step 3 or in the configuration write request procedure) 2. initialize the content of the service request table. 3. initialize the service request pointer (srp) with the address of service request table by performing a direct write to the service request pointer register. 4. start the execution by writing the tabl e length into to the service request length register by performing a direct write. 5. if other service request table is required, the host must poll the service request length register by performing a direct read and check the srq_len field. if this fields is not zero, the cx 28560 did not complete the execution of the last service request table. the nu mber written in th e srq_len indicates how many configuration write commands (i.e., table entries) are pending for execution. while processing these commands, the cx28560 generates a sack interrupt for each command in whic h the sackien bit was set. when srq_len becomes 0, the host may start from step one in configuration write request procedure , whereas prior to a new ex ecution either frees the memory which was allocated for the prio r service request table or uses the same memory as a pool memory. the registers initialized th rough the service request mechanism are as follows: a. global configuration [1] (one per chip) b. ebus configuration [1] (one per chip) c. rslp channel configuration [2047] (one for each channel which is going to be activated) d. rslp max. message length [3] (three registers) e. rbuffc configuration [2047] (one for each channel which is going to be activated) f. rbuffc flexiframe memory [1] (one per chip) g. rbuffc data fifo size [1] (one per chip) h. rbuffc fragment size [1] (one per chip) i. rbuffc slot time [1] (one per chip) j. rbuffc flexiframe control [1] (one per chip) k. rsiu time slot/group ma p [8192] (for each time slot that is going to be used)
28560-DSH-001-B mindspeed technologies? 6 - 7 advance information cx28560 data sheet functional description l. rsiu group map [8192] (for each group time slot that is going to be used) m. rsiu time slot/group map pointer allocation [32] (one per port) n. rsiu group map pointer allocation [64] (one per group required) o. rsiu group state register [512] (for each group, the relevant state register should be set to zero). p. rsiu port configuration [32] (for each port that should operate, this command activates the port) q. tslp channel configuration [2047] (one for each channel that is going to be activated) r. tbuffc configuration [2047] (one for each channel that is going to be activated) s. tbuffc flexiframe memo ry [1] (one per chip) t. tbuffc data fifo size [1] (one per chip) u. tbuffc fragment size [1] (one per chip) v. tbuffc slot time [1] (one per chip) w. tbuffc flexiframe control [1] (one per chip) x. tsiu time slot/group map [8192] (for each time slot that is going to be used) y. tsiu group map [8192] (for each group time slot that is going to be used) z. tsiu time slot/group map pointer allocation [32] (one per port) aa. tsiu group map pointer allocation [64] (one per group required) ab. tsiu group state register [512] (for each group, the relevant state register should be set to zero). ac. tsiu port configuration [32] (for each port which should operate, this command activates the port) ad. transmit pos-phy thresholds register [1] (once per chip) ae. transmit pos-phy control regi ster [1] (once per chip) af. receive pos-phy control register [1] (once per chip) 6. perform a ch_act service request and wait for sack when the sackien bit is set. 7. for each channel that must be activated , the host prepares a ch_act service request and inserts it into the service re quest table. the host may decide if to activate all channels by writing the se rvice request queries into one single service request table or by splitting the service request commands into one or more tables. for each ch_act service request the host follows the same steps as were specified at 1?5 in this section.
6-8 mindspeed technologies? 28560-DSH-001-B advance information functional description cx28560 data sheet 6.2 channel operations 6.2.1 channel activation after the previous levels of configuratio n are completed, indi vidual channels are ready to be activated. service requests ar e used to activate channels. each channel consists of a transmit and a receive direct ion. each direction is independent of the other and maintains its own state machines, configuration registers, and internal resources. to activate both transmit and rece ive directions of a channel, two separate service requests are required, one directed to the transmit dire ction and one to the receive. the cx28560 responds to each se rvice request with the sack interrupt descriptor, which notifies the host that the task was initiated. note that the sack interrupt will only be generated if the sack ien bit is asserted in the service request descriptor. if the channel to be activated requires a new flexiframe, the new flexiframe should first be written into the cx28560 (via the service request mechanism). once the system has detected that the new flexiframe is in place and in use (either by receiving a nfframe interrupt, or detecting that the nfframe bit has been set to zero by the cx28560), a channel that has now been includ ed in the flexiframe can be activated. not writing the new flexiframe first may cause overflows in the receive direction. channel activation should only be performed on a non-active channel. attempting to reactivate a channel by sending an activate command to an already active channel will produce undefined behavior by the cx28560. a channel has not been successfully deactivated until the end of comma nd (eoc) interrupt is received. note: the notification to the host that the channel activation was completed is an eoc interrupt. this acknowledges the host that the srq was completed. the sack command signifies that the cx28 560 is ready to receive the next command, but not that the activation was completed.
28560-DSH-001-B mindspeed technologies? 6 - 9 advance information cx28560 data sheet functional description 6.2.1.1 transmit channel activation the following describes what the cx28560 does when a transmit channel is activated: 1. the internal channel fifo is flushed in preparation for new messages. 2. all counters connected to the channel being activated are zeroed in preparation for a new channel connection. 3. abort codes (all 1s) are transmitted until new data arrives for transmission. 4. once fragments start arriving for the newly activated channel, the cx28560 assumes that these fragments are the star t of a new packet. the internal buffer threshold is used to ensure that enou gh data to start transmitting without causing an underrun. once the threshold has been crossed, transmission of messages can begin. 5. if the channel is configured in hdlc mode, the cx28560 transmits the message as hdlc frames, otherwise, the data is transmitted as if starting from a first time slot in the serial port frame. 6. once a complete message has been tr ansmitted, if the eom interrupt is enabled, an eom interrupt is generated, and the cx28560 transmits inter- message idle codes according to the fragment header received. 7. go to 3. 6.2.1.2 receive channel activation the following describes what the cx28560 do es when a receive channel is activated: 1. the internal channel fifo is flushed in preparation for new messages. 2. all counters connected to the channel being activated are zeroed in preparation for a new channel connection. 3. in the case of a channel configured for hdlc processing, data is discarded until an opening flag sequence is detected . in the case of a transparent channel, data is discarded until the first time slot of a frame. 4. for an hdlc channel, the data is pr ocessed according to the hdlc standard, or for transparent channels, the data is simply collected. 5. once either enough data for a fragment has been collated in the channel?s fifo or an end of message is detected, a fragm ent header is attached to the fragment data, and the complete fragment is passed to the host over the pos-phy interface. 6. once a complete message has been receiv ed, if the eom interrupt is enabled, an eom interrupt is generated, and the cx28560 scans the idle codes received between messages. 7. if the idle code has been swapped since the previous message, and the chic/ chabt interrupt is enabled, a chic/chabt interrupt is generated. chic is generated when the change was to hdlc flags, chabt is generated when the change was to an all 1s intermessage fill. 8. go to 3.
6-10 mindspeed technologies? 28560-DSH-001-B advance information functional description cx28560 data sheet 6.2.2 channel deactivation after the channel has been activated, channel deactivation via a service request suspends activity on an individual channe l direction. each channel consists of a transmit and a receive direction. each di rection is independent of the other and maintains its own state machines and configuration registers. to deactivate both the transmit and receive directions of a chan nel, two separate service requests are required, one directed towards the transmit and one to the receive. the cx28560 may respond to each service request with the sack interrupt descriptor, which notifies the host that the task was initiated. note that the sack interrupt will only be generated if the sackien bit is asserted in the service request descriptor. note: the notification to the host that the task was completed is an eoc interrupt. this acknowledges the host that the srq was completed. a channel deactivation is an asynchronous command from the host interface to a transmit or receive section of a channel to suspend processing and halt memory transfers to/from the host. 6.2.2.1 transmit channel deactivation the following describes what the cx28560 does when transmit channel is deactivated: 1. the current message processing is terminated destructively. that is, data can be lost and messages prematurely aborted. the cx28560 does not give any indication of a lost message directly to the host, but does increment the aborted messages counter. 2. internal fifos are flushed and the data is lost. 3. the tslp is responsible for handling outbound bits when the serial port is asynchronously disabled. the data output pin, tdat, is held at logic 1. any data received by the cx28560 while a channel is deactivated is discarded. 4. the transmit channel remains in the suspended state until the channel is activated. the current channel dire ction configuration is maintained. note: counters are automatically zeroed on de activation, activation and one-second pulses. 6.2.2.2 receive channel deactivation the following describes what the cx28560 do es when receive channel is deactivated: 1. current message processing is terminated destructively. that is, data can be lost and messages prematurel y aborted. the cx28560 does not give any direct indication of th e lost messages. 2. internal fifos are flushed and all data is lost. 3. the rslp is responsible for handling inbound bits when the serial port is asynchronously disabled. data tr ansfers to the host are halted. 4. the receive channel remains in the su spended state until the channel is activated. the current channel dire ction configuration is maintained. note: counters are automatically zeroed on de activation, activation and one-second pulses. 6.2.3 channel reactivation channel reactivation is not supported. to re set a channel, it must first be deactivated, and then, once the end of command (eoc) interrupt has been received, activated.
28560-DSH-001-B mindspeed technologies? 6 - 11 advance information cx28560 data sheet functional description 6.3 port operations 6.3.1 unmapped time slots the host can stop the cx28560 from proces sing certain time slot s regardless of the channel activation/deactivati on/ reactivation commands. this can be performed by programming time slots in rsiu time sl ot configuration and tsiu time slot configuration to indicate that the specific time slots are not mapped. (see rts_enable and tts_enable bit fields in chapter 5.0 , rsiu time slot configuration register and tsiu time slot configuration register, respectively). note: the tdat signal is either set to logi c 1 or three-state acco rding to bit tritx in chapter 5.0 , tsiu time slot configuration register. 6.3.2 enabling a port the procedure required for enabling a receive port and a transmit port is identical. a port can be enabled by writing a 1 to th e enbl bit in the siu port configuration register. once a port has been enabled, changing the time slot map allocation to the port (i.e., the startad_ts and endad_ts fields) is not allowed; however, changing the mapping of the time slots to channels is allowed the new port configuration is written to the siu port configuration register. when a port is configured to work in ts bus mode and ds0 extraction is configured within the port (i.e., that the groups of ch annels have been assigned to one or more time slots by a group number), a special pr ocedure is required. before enabling the port, the group state machines of th e groups included in the port must be reset. resetting the group state machines is done by writing the value 0 to all 32 bits in the group state register (see chapter 5.0 , rsiu and tsiu) for each group in each port to be enabled. 6.3.3 disabling a port the procedure required for disabling a receiv e port and a transmit port is identical. a port can be disabled by writing a 0 to the enbl bit in the siu port configuration register. once a port has been disabled, changing the time slot map allocation to the port (i.e., the startad_ts and endad_ts fields) is allowed.
6-12 mindspeed technologies? 28560-DSH-001-B advance information functional description cx28560 data sheet
28560-DSH-001-B mindspeed technologies? 7 - 1 advance information 7.0 basic operations the two main channel protocols, hdlc and transparent mode, are described in subsequent sections of this chapter. hdl c and transparent mode operations perform protocol-specific processing of their respect ive input and output serial bit streams, and behave differently in their treatmen t of those bit streams during abnormal conditions. 7.1 protocol-independent operations from a functional viewpoint, many of the cx28560 operations are protocol- independent, though some behavior may di ffer between the transmitter and receiver. the protocol-independent operations described below apply to all event and error handling:  during buffer controller, slp channel protocol, and siu serial port operations, an event or error may occur that indica tes the status of the message transfer process or that affects the outcome of the overall message transfer process. unless masked, all such events and er rors cause the cx28 560 to write an interrupt descriptor to the shared memory interrupt queue. interrupt descriptors identify the error or even t condition, the tran smit or receive direction, and the affected channel or port number.  if the cx28560 suspends a channel?s op eration or deactivates a channel, the host must perform a channel reactivation by issuing a channel activation service request. this is referred to as ?requiring reactivation.? 7.1.1 transmit the cx28560 initiates data transfer to th e serial interface only if the following conditions are true:  txenbl bit set to 1 in chapter 5.0 , tsiu port configuration register.  transmit channel is mapped to time slot(s), which are enabled in the port?s chapter 5.0 , tsiu time slot configuration register.  transmit channel has been activated by a host service request.  the channel number appears at least once in the active flexiframe. if txenbl bit is set to 0 (transmit port disabled), the serial data output signal is placed in high-impedance three-state. if tx enbl = 1 (port enabled) and a time slot is disabled, the corresponding time slot?s transm itter output is either a three-state or all 1s signal depending on the state of the tritx bit field in the port?s tsiu port configuration register (see chapter 5.0 ).
7-2 mindspeed technologies? 28560-DSH-001-B advance information basic operations cx28560 data sheet note: if txenbl = 1 and the port is configured in any channelized mode (i.e., not unchannelized), until the first tsync/t stb pulse is detected, that port outputs either a three-state signal or an all 1s signal, depending on the state of the tritx bit field. 7.1.2 receive the receiver processes data from the serial interface only if all of the following conditions are true:  rxenbl bit is set to 1 in the port?s rsiu port configuration register.(see chapter 5.0 )  receive channel is mapped to time slot(s ), that are enabled in the port?s rsiu time slot configuration register. (see chapter 5.0 )  receive channel has been activated by a host via service request.  the channel number appears at least once in the active flexiframe. if any of the first three above conditions is not true, the receiver ignores the incoming data stream. if the last condition is not true , eventually an overfl ow will occur for the channel. data is transferred to the system in frag ments over the pos-phy interface, prefixed with a fragment header. the first data is sent for a channel after act ivation as soon as a complete fragment has been completed. 7.2 hdlc mode the cx28560 supports three hdlc modes. the modes are assigned on a per-channel and direction basis by setting the protocol bit field within the rslp/tslp channel configuration registers. the hdlc modes are as follows:  hdlc-nocrc: hdlc support, no crc  hdlc-16crc: hdlc support, 16-bit crc  hdlc-32crc: hdlc support, 32-bit crc hdlc protocol-specific support in the transmitter includes the following:  generate opening/cl osing/shared flags  zero-bit insertion after five consecutive 1s are transmitted  generate pad fill between frame s and adjust for zero insertions  generate 0-, 16- or 32-bit crc (i.e., fcs)  generate abort sequences upon fifo unde rflow condition or as instructed on a per-message basis by asserting the error line on the pos-phy or by setting the abort bit in the fragment header of the last fragment of the packet.  data inversion of all bits (including flags and pad fill characters) hdlc protocol-specific support in the receiver includes the following:  detection and extraction of opening/closing/shared flags  detection of shared-0 between successive flags  zero bit extraction after five consecutive 1s are received  detect changes in pad fill idle codes
28560-DSH-001-B mindspeed technologies? 7 - 3 advance information cx28560 data sheet basic operations  check and extract 0-, 16- or 32-bit fcs  check frame length  check for octet alignment  check for abort sequence reception  after channel activation, check for the first flag character to be received and generate a chic interrupt in the transmit direction, the fragment head er of a message specif ies intermessage bit- level operations. specifically, when the eom bit field is set to 1 within the fragment header, it signifies that th e present fragment represents the last fragment for the current message being transm itted and the bit fields ic and padcnt take effect. these bits are described in this chapter, section 7.2.5 . 7.2.1 frame check sequence the cx28560 is configured to calculate and insert either a 16- or 32-bit frame check sequence (fcs) for hdlc packets, provided the packet length contains a minimum of 2 octets. the fcs is always calculated over the entire packet length. for all hdlc modes that require fcs calcula tion, the polynomials used to calculate fcs are according to itu-t q.921 and iso 3309-1984. crc-16: x 16 + x 12 + x 5 + 1 crc-32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 7.2.2 opening/closing flags for hdlc modes only, the cx28560 supports the use of opening and closing message flags. the 7eh (01111110b) flag is the opening and closing flag. an hdlc message is always bounded by this flag at the beginning and the end of the message. the cx28560 supports receiving a shared flag where the closing flag of one message can act as the opening of the next message . the cx28560 also supports receiving a shared-zero bit between two flags?that is, the last zero bit of one flag is used as the first zero bit of the next flag. receiving a shared zero between the fcs and the closing flag is not supported. the cx28560 can be configured to transm it a shared flag between successive messages by configuring the bit field padc nt in each transmit fragment header (specifically the last fragment header of a message). the cx28560 does not transmit shared-zero bits between successive flags. 7.2.3 abort codes seven consecutive 1s constitute an abort code. receiving the abort code causes the current frame processing to be aborted and further data tr ansfer into shared memory for that message is terminated. after detecting the abort code, the cx28560 enters a scan mode, which searches for a new opening flag character. notification of this detected condition is pr ovided in the last fragment header of the message and/or an interrupt descriptor indicating the error condition abort flag termination.
7-4 mindspeed technologies? 28560-DSH-001-B advance information basic operations cx28560 data sheet in cases where received idle codes transition to an abort code, an interrupt descriptor is generated toward the host (if enabled in rslp channel configuration register?see chapter 5.0 ), indicating the informat ional event change to abort code. all received abort codes are discarded. note: seven 1s are the abort condition the cx28560 checks for while receiving a message, but the criteria for detection and generation of a change to abort code interrupt is equal to 14 consecutive 1s. 7.2.4 zero-bit insertion/deletion the cx28560 provides zero-bit insertion and deletion when it encounters five consecutive 1s within a frame. in the receiver, the zero-bit is removed (discarded). in the transmitter, the zero-bit is insert ed after each sequence of five 1s. 7.2.5 message configur ation bits?hdlc mode the last fragment of a transmit message is pref ixed by a fragment h eader that contains message configuration bits to specify what data pattern is transmitted after the end of a current message and its respective closing fl ag have been transmitted. the bits are specified as follows:  idle code specification, ic  inter-message pad fill count, padcnt  send an abort sequence, abrt or assert err line on pos-phy note: message configuration bits are also used in transparent mode with slightly different meanings. for details, see idle code. 7.2.5.1 idle code the idle code (ic) specification allows one of a set of idle codes to be chosen to be transmitted after the current me ssage in case the next message is not available to be transmitted or intermessage pad fill is requested via padcnt. 1. ic = 0: flag pad fill 2. ic = 1: all ones pad fill 3. ic = 2: all zeroes pad fill 7.2.5.2 intermessage pad fill the pad count (padcnt) specifi cation allows pad fill octets (a sequence of one or more specified idle codes) to be tran smitted between messages. padcnt is the minimum number of fill octets to be tran smitted between the closing flag of one message and the opening flag of the next message in the following manner: 1. padcnt = 0: shared open/close flag 2. padcnt = 1: separate open/c lose flags, no idle code 3. padcnt = 2: separate open/close flags, at least one idle code 4. etc.
28560-DSH-001-B mindspeed technologies? 7 - 5 advance information cx28560 data sheet basic operations 7.2.5.3 ending a message with an abort or sending an abort sequence if the abort and the eom indications are set in a fragment header, the cx28560 interprets it as a request to end an in-pro gress message with the abort sequence. if the previous fragment header contained an e nd-of-message (eom) indication, the abort request is ignored. if the previous fragment header was not eom (i.e., a transmit message was in-progress), an abort code sequence is transmitted to end that partially sent message. transmission of an abort code sequence is defined as 16 consecutive 1s. 7.2.6 transmit events transmit events are informational in nature and do not require channel recovery actions. 7.2.6.1 end of message (eom) reason:  tslp has transmitted (actually, transferre d to the tsiu) the last bit of a data buffer (excluding the fcs and closing fl ag) and the transmit fragment header signifies that the fragment containe d an end of a message (eom = 1). effects:  txeom interrupt (if eomien = 1 in chapter 5.0 , tslp channel configuration register).  tslp and tbuffc continue normal processing. if the tbuffc does not receive more data from the system ov er the pos-phy before the tslp needs to output the next data bit, tslp outp uts another octet of flag or idle code. 7.2.6.2 transmit cofa recovery (tcrec) reason:  tsiu terminates the internal cofa co ndition due to the arrival of a tsync/ tstb pulse followed by at least the assign ed number of time slots for this port without another unexpected tsync/tstb pulse. this interrupt will also be generated when a suitable number of time slots have passed after a cofa interrupt generated by the first sync pulse. effects:  tcrec interrupt (if cofaien = 1 in chapter 5.0 , tsiu port configuration register). channel-level recovery actions:  transmit channel reactivation should be performed. 7.2.7 receive events receive events are informational in nature and do not require channel recovery actions. 7.2.7.1 end of message (eom) reason:  rslp has detected the end of a message (closing flag or an error condition).
7-6 mindspeed technologies? 28560-DSH-001-B advance information basic operations cx28560 data sheet error conditions include: overflow, cofa, oof, abort, too long, alignment and fcs error. effects:  if there were no errors, rxeom interrupt (if eomien = 1 in chapter 5.0 , rbuffc channel configuration regist er). if there were errors, rxeom interrupt (if errien = 1 in chapter 5.0 , rbuffc configuration register and chapter 5.0 , tbuffc configuration register).  rbuffc sets eom = 1 in receive fragment header.  rbuffc and rslp continue normal processing. 7.2.7.2 change to abort code (chabt) reason:  rslp detected received data changed fr om flag (7eh) octets to abort code (zero followed by 15 consecutive 1s). effects: 7.2.7.3 chabt interrupt (if idleien = 1 in chapter 5.0 , rslp channel configuration register).  rslp and rbuffc continue normal processing. 7.2.7.4 change to idle code (chic) reason:  rslp detects received data changed to flag (7eh) oc tets. the cx28560 requires detection of three consecutive flags before a chic event is generated. effects:  chic interrupt (if idleien = 1 in chapter 5.0 , rslp channel configuration register).  rslp and rbuffc continue normal processing. note: after channel activation/reactivation, the first flags detected on the line generate a chic interrupt. 7.2.7.5 frame recovery (frec) or generic serial port (sport) interrupt reason:  rsiu detects the serial interface roof signal transition from an out-of-frame (roof = 1) to an in-frame (roof = 0) condition. if the roof signal is programmed for use as an out-of-frame in dicator, this frame recovery event (roof returning low) generates a frec interrupt. if the roof signal is used as a general-purpose interrupt input, this event generates a sport (serial port) interrupt. effects:  frec/sport interrupt (if oofien = 1 in chapter 5.0 , rsiu port configuration register).  rslp and rbuffc continue normal processing.
28560-DSH-001-B mindspeed technologies? 7 - 7 advance information cx28560 data sheet basic operations 7.2.7.6 receive cofa recovery (rcrec) reason:  rsiu terminates the internal cofa co ndition due to the arrival of a rsync/ tstb pulse followed by at least the assign ed number of time slots for this port without another unexpected rsync/tst b pulse. this interrupt is also generated after the cofa caused by the first sync pulse received on a port. effects:  rcrec interrupt (if cofaien = 1 in chapter 5.0 , rsiu port configuration register).  rslp and rbuffc continue normal processing. 7.2.8 transmit errors transmit errors are service-af fecting and require a corrective action by a controlling device (i.e., the host) to resu me normal channel processing. 7.2.8.1 transmit underrun (buff) the cx28560 needs to send more data towa rds the tsiu for an in-progress transmit message, but the internal channel fifo is empty. reasons:  degradation of the host subsystem or application software.  host applied back-pressure on the flow conductor pos-phy bus causing reports of buffer levels not to reach the host. effects:  txbuff interrupt (if buffien = 1 in chapter 5.0 , tslp channel configuration register).  transmit channel enters deactivate stat e where the tslp transmits a repetitive abort sequence of 16 consecutive 1s.  transmit output is three-stated. channel-level recovery actions:  transmit channel reactivation is required. 7.2.8.2 transmit change of frame alignment (cofa) tsync or tstb input signal transitions from low to high, but at an unexpected time in comparison to the internal frame sy nchronization flywheel mechanism. cofa errors are only applicable to channelized ports (i.e., unchannelized ports ignore the tsync input). frame synchronization indicate s the expected location of the first bit of time slot 0 on the transmit serial data output. lacking frame synchronization, the transmitter cannot map or align time slots. this error affects all active channels on the respective port. note that a similar error in tsbus mode within the group map will not cause an interrupt to be generated. reason:  signal failure, glitch or realignment cau sed by the physical interface sourcing the tsync/tstb input signal.
7-8 mindspeed technologies? 28560-DSH-001-B advance information basic operations cx28560 data sheet effects:  causes serial interface to enter cofa condition until a tsync/tstb pulse arrives and is followed by at least the assigned number of time slots for this port, without another unexpected tsync/tstb pulse.  for every active channel on the respecti ve port, tslp places channels into the deactivate state. wherein, tslp send s a repetitive abort sequence of 16 consecutive 1s.  transmit cofa interrupt (if cofaien = 1 in chapter 5.0 , tsiu time slot configuration register). note: cofa interrupt is generated immediatel y. to synchronize the host?s response to a cofa condition, a cofa recovery interrupt is also provided.  transmit output is three-stated. channel-level recovery action:  transmit channel reactivation is required on receiving the transmit cofa recovery (crec) interrupt. 7.2.8.3 buffer controller ch annel fifo overflow (bovflw) reason:  degradation of the host subsystem or application software.  incorrect calculation of the size of internal fifo required. effects:  semi-deactivation of the channel. no fu rther data will be transmitted on the channel, and, if the overflow occurred mid-message, the last message in the internal fifo that was stored before the overflow occurred will be aborted. channel-level recovery actions:  the affected channel should be deac tivated and reactivated if required. 7.2.9 receive errors receive errors are service-affecting, but do not require corrective action by the host to resume normal processing. 7.2.9.1 receive overflow (buff) the rslp receives a signal from the rsiu th at more data bits are available to be stored, but the rslp channel fifo is already full. reasons:  degradation of host subsystem performance. this will be caused by host assertion of back-pressure on the data pos-phy, not allowing the rbuffc to transmit the data to the host , thus filling the receive buffers.  size of rbuffc internal fifo insufficient.
28560-DSH-001-B mindspeed technologies? 7 - 9 advance information cx28560 data sheet basic operations effects:  rxbuff interrupt (if buffien = 1 in chapter 5.0 , rslp channel configuration register).  if a receive message was in progress, that message is marked as errored with an overflow error code. the rslp scans fo r the opening flag of the next hdlc message and any subsequent receive messa ges are discarded until the internal fifo has room to accept more rsiu data. notice the channel remains active and channel recovery is automatic.  when the in-progress message reaches the top of the internal fifo, the entire hdlc message (before the overflow occurr ed) is transmitted to the host. in the last fragment the status will be set as follows: eom = 1, error = buff.  rxerr interrupt is generated, if errien is set in chapter 5.0 , rbuffc configuration register and chapter 5.0 , tbuffc configuration register, indicating a rxbuff error overflow.  rbuffc is not affected and continues to transfer data for th is channel to the system. channel-level recovery actions:  if possible, increase internal fifo size assigned to this channel. for this action, all channels must first be deactivated. notice that channel react ivation is not required. 7.2.9.2 receive change of frame alignment (cofa) rsync or tstb input signal transitions from low to high, but at an unexpected time compared to the frame synchronization flyw heel mechanism. cofa errors are only applicable to channelized ports (i.e., un channelized ports ignore the rsync/tstb input). frame synchronization in dicates the expected location of the first bit of time slot 0 on the receive serial data input. lacking frame synchronization, the receiver cannot map or align time slots. this error affects all active channels on the respective port, but does not require a host recovery ac tion. note that a similar error in tsbus mode within the group map will not ca use an interrupt to be generated. reason:  signal failure, glitch, or realignment ca used by the physical interface sourcing the rsync or tstb input signal.  first sync to arrive at a port (this cofa interrupt should be treated as a report of an event rather than as an error). effects:  causes serial interface to enter cofa condition until the rsync/tstb pulse is followed by at least the assigned numb er of time slots for this port, without another unexpected rsync/tstb pulse.  if a receive message was in-progress, that message is marked as errored. rslp scans for the opening flag of the next hdlc message and any subsequent receive messages are discarded until th e internal cofa co ndition has ended.  when the in-progress message reaches the top of the internal fifo, the entire hdlc message is copied to shared memory buffers and receive buffer status descriptors are written with on r = host and error = cofa (if
7-10 mindspeed technologies? 28560-DSH-001-B advance information basic operations cx28560 data sheet inhrbsd = 0 in chapter 5.0 , rbuffc configuration register and chapter 5.0 , tbuffc configuration register).  receive cofa interrupt is generated (if cofaien = 1 in chapter 5.0 , rsiu port configuration register). note that a tstb change of alignment causes both a receive and a transmit cofa in terrupt, since tstb applies to both transmit and receive directions simultaneously.  normal operations continue after the cofa condition ends.  rbuffc is not affected and continue s shared memory buffer processing. channel-level recovery actions:  none required. 7.2.9.3 out-of-frame (oof) out-of-frame or loss-of-frame indicates the entire receive serial data stream is invalid and all data input from that port should be ignored. reason:  roof input pin is asserted (high) because the attached physical layer device is unable to recover a valid, framed signal. effects:  oof interrupt (if oofien = 1 and oofabt = 1 in chapter 5.0 , rsiu port configuration register).  if bit field oofabt = 0, rslp and rbu ffc continue as if no errors and transfer received data to the host normally.  if bit field oofabt = 1 and a receive message is in-progress, the current message is ended with oof status and rs lp scans for the opening flag of the next hdlc message. when the in-progr ess message reaches the top of the internal fifo, the message is transferre d to the host and the last fragment header of the message is written error = oof.  rbuffc is not affected and continue s shared memory buffer processing.  receive channels recover automati cally when the roof input pin is deasserted (low), indicating the oof condition has ended. channel-level recovery actions:  none required. 7.2.9.4 frame check sequence (fcs) error in this case, the frame check sequence (f cs) which the cx28560 calculated for the received hdlc message does not match the fcs located within the message. reason:  bit errors duri ng transmission. effects:  eom interrupt with rxfcs erro r status, (if errien = 1 in chapter 5.0 , rbuffc configuration register and chapter 5.0 , tbuffc configuration register).  when the message reaches the top of the internal fifo, the hdlc message is transferred to the host and the last fr agment header is written with error = fcs.
28560-DSH-001-B mindspeed technologies? 7 - 11 advance information cx28560 data sheet basic operations  the rslp scans for the opening flag of the next hdlc message.  rbuffc is not affected and continues to transfer message data to the host. channel-level recovery actions:  none required. 7.2.9.5 octet alignment error (align) the hdlc message size after zero-bit extr action was not a multiple of 8 bits. reasons:  bit errors duri ng transmission.  incorrect message transm ission from distant end. effects:  eom interrupt with rxalign er ror status, (if errien = 1 in chapter 5.0 , rbuffc configuration register and chapter 5.0 , tbuffc configuration register).  when the message reaches the top of the internal fifo, the hdlc message is transferred to the host and the fragment header is written with error = align.  the rslp scans for the opening flag of the next hdlc message.  rbuffc is not affected and continues to transfer message data to the host. channel-level recovery actions:  none required. 7.2.9.6 abort termination (abt) the receiver detects an abort sequence from the distant end. an abort sequence is defined as any zero followed by 15 consecutive 1s. reasons:  distant end failed to complete transmission of the hdlc message.  path conditioning has replaced the norm al channel content with an all 1s pattern, due to a network alarm condition. effects:  eom interrupt with rxabt error status, (if errien = 1 in chapter 5.0 , rbuffc configuration register and chapter 5.0 , tbuffc configuration register).  when the message reaches the top of the internal fifo, the hdlc message is transferred to the host with the last fr agment header of the message written as error = abt.  the rslp scans for the opening flag of the next hdlc message.  rbuffc is not affected and continues to transfer message data to the host. channel-level recovery actions:  none required.
7-12 mindspeed technologies? 28560-DSH-001-B advance information basic operations cx28560 data sheet 7.2.9.7 long message (lng) the received hdlc message length is determined to be greater than the maximum allowable message size per the maxsel bit field in chapter 5.0 , rslp maximum message length register. reason:  incorrect message transm ission from distant end. effects:  eom interrupt with rxlng erro r status (if errien = 1 in chapter 5.0 , rbuffc configuration register and chapter 5.0 , tbuffc configuration register).  when the message reaches the top of the internal fifo, the hdlc message? up to the maximum legal length?is transferred to the host, and the last fragment header of the message is written with error = lng.  the rslp scans for the opening flag of the next hdlc message.  rbuffc is not affected and continues to transfer message data to the host. channel-level recovery actions:  none required. 7.2.9.8 short message (sht) the total received hdlc message size (between open/close flags) is determined to be less than the number of fcs bits specifie d for that channel plus one octet. for example, a channel configur ed for 16-bit fcs must re ceive a minimum of three octets?one octet of payload and two octets of fcs?to avoid a short message error. in this example, receiving only two octets is considered a short message. note: any message that ends with an error (any error except an overflow) and for which the entire message (regardless of its length) still resides in the internal slp buffer (meaning no data has yet been transferred to the internal channel fifo), the cx28560 generates a sht inte rrupt and does not transfer any of that message to a shared memory buffer. in this case, no other indication is given for the errored message. note: because the rxsht interrupt in this case is reported immediately, its interrupt descriptor can arrive in the shared me mory interrupt queue before an earlier message that remains queued in the internal buffc channel fifo. hence, interrupts from these two messages may appe ar out of sequence with respect to their actual order of arrival. reasons:  bit errors duri ng transmission.  incorrect message transm ission from distant end. effects:  rxsht interrupt (if idleien = 1 in chapter 5.0 , rslp channel configuration register).  rslp resumes scanning for opening flag of the next hdlc message.
28560-DSH-001-B mindspeed technologies? 7 - 13 advance information cx28560 data sheet basic operations  rbuffc is not affected and continues to transfer message data to the host. channel-level recovery actions:  none required. 7.3 transparent mode the cx28560 supports a completely transpar ent mode where no distinction is made between information and non-information bits in the channel bit st ream. this mode is assigned on a per-channel and per-direct ion basis by the protocol bit field in chapter 5.0 , rslp channel configuration register and chapter 5.0 , tslp channel configuration register. 7.3.1 message configuratio n bits?transparent mode the transmit fragment header contains a group of bits that specify the data to be transmitted after the end of a transparent mode message. the bits are specified as follows:  idle code specification, ic  intermessage pad fill count, padcnt  send an abort sequence. note: message configuration bits are also us ed in hdlc mode, but their meaning is slightly different. refer above to message configuration bits? hdlc mod e. 7.3.1.1 idle code idle code (ic) bit field selects one of a set of idle pad fill octets to be sent after the current message is transmitted in the event the next fragment has not been received or inter-message pad fill is requested via padcnt. 1. ic = 0: all ones pad fill. 2. ic = 1: hdlc flag pad fill. 3. ic = 2: all zeroes pad fill. 7.3.1.2 intermessage pad fill pad count (padcnt) bit field specifies how many pad fill octets (selected by ic) are transmitted between messages. padcnt speci fies the minimum number of pad fill octets plus one, as follows: 1. padcnt = 0: one ic 2. padcnt = 1: two ics 3. padcnt = 2: three ics 4. etc. 7.3.1.3 ending a message with an abort or sending an abort sequence when the err line on the data pos-phy is asserted, the cx28560 interprets this as a request to end an in-progress message wi th the abort sequence. abort sequence for transparent mode is defined to be a se quence of all 1s. th e abort sequence is terminated only when new data is received for the channel. in th is case, the cx28560
7-14 mindspeed technologies? 28560-DSH-001-B advance information basic operations cx28560 data sheet resynchronizes the start of the next message transmission to the time slot marked as the first time slot on that channel. if an abort is requested, and the previous message had been aborted and no new data had been received, the abort command is simply ignored and the cx28560 awaits new data. the host may set eom = 1 in any transmit fra gment to separate this transparent mode ?message? from the next message, according to the ic and padcnt bit fields. unlike hdlc mode, the number of pad fill octets transmitted equals padcnt + 1, and no flag characters are inserted. 7.3.2 transmit events transmit events are informational in nature and require no recovery actions. 7.3.2.1 end of message (eom) reason: tslp has transmitted (actually, transferred to the tsiu) the last bit of a data buffer and the transmit fragment header signified the end of a message with bit field eom = 1. effects:  txeom interrupt (if eomien = 1 in chapter 5.0 , tslp channel configuration register).  tslp and tbuffc continue normal message processing. if the tbuffc does not receive more data before the internal channel fifo becomes empty and the tslp needs to output another data bit, tslp outputs pad fill octets until more data is available. 7.3.3 receive events receive events are informational in na ture and require no recovery actions. 7.3.3.1 end of message (eom) reason:  rslp must force an end of a message du e to a receive error condition. error conditions include overflow, cofa, or oof. effects:  rxeom interrupt (if errien = 1 in chapter 5.0 , rsiu time slot configuration register) with the appropriate rxerr status.  rbuffc sets bit field eom = 1 in receive buffer status descriptor (if inhrbsd = 0 in chapter 5.0 , rsiu time slot configuration register).  rslp continues normal processing after the error condition has ended.  rbuffc is not affected and continue s shared memory buffer processing.
28560-DSH-001-B mindspeed technologies? 7 - 15 advance information cx28560 data sheet basic operations 7.3.3.2 frame recovery (frec) reason:  siu detects the serial interface has transi tioned from an out-of-frame to an in- frame condition. if the r oof pin is used as an out-of-frame indication, a frec interrupt is generated. if the roof pin is used as a general purpose interrupt input, a sport (seria l port) interrupt is generated. effects:  frec/sport interrupt (if oofien = 1 in chapter 5.0 , rsiu port configuration register).  rslp and rbuffc continue normal processing. 7.3.3.3 receive cofa recovery (rcrec) reason:  siu terminates the internal cofa condition due to a rsync/tstb pulse followed by at least the assigned number of time slots for this port without another unexpected rsync/tstb pulse. effects:  rcrec interrupt (if cofaien = 1 in chapter 5.0 , rsiu port configuration register).  rslp and rbuffc continue normal processing. 7.3.4 transmit errors transmit errors are service-affecting and re quire a corrective action by the host to resume normal processing. 7.3.4.1 transmit underrun (buff) same as hdlc mode. reasons:  degradation of the host subsystem or application software.  host applied back-pressure on the flow conductor pos-phy bus causing reports of buffer levels not to reach the host. effects:  txbuff interrupt (if buffien = 1 in chapter 5.0 , tslp channel configuration register).  transmit channel enters deactivate state, wherein tslp sends a repetitive all 1s sequence. channel-level recovery actions:  transmit channel reactivation is required.
7-16 mindspeed technologies? 28560-DSH-001-B advance information basic operations cx28560 data sheet 7.3.4.2 transmit change of frame alignment (cofa) reason:  signal failure, glitch, or realignment ca used by the physical interface sourcing the tsync/tstb input signal. effects:  causes serial interface to enter cofa condition until a tsync/tstb pulse arrives and is followed by at least the assigned number of time slots for this port, without another unexpected tsync/tstb pulse.  for every active channel on the respecti ve port, tslp places channels into the deactivate state, wherein tslp sends a repetitive all 1s sequence.  transmit output is three-stated. channel-level recovery actions:  transmit channel reactivation is required. 7.3.4.3 buffer controller ch annel fifo overflow (bovflw) reason:  degradation of the host subsystem or application software.  incorrect calculation of the size of internal fifo required. effects:  semi-deactivation of the channel. no fu rther data will be transmitted on the channel, and, if the overflow occurred mid-message, the last message in the internal fifo that was stored before the overflow occurred will be aborted. channel-level recovery actions:  the affected channel should be deac tivated and reactivated if required. 7.3.5 receive errors receive errors are service-affecting and may require a corrective action by the host to resume normal processing. 7.3.5.1 receive overflow (buff) same as hdlc mode. reasons:  degradation of the host subsystem performance. this will be caused by host assertion of back-pressure on the data pos-phy, not allowing the rbuffc to transmit the data to the host , thus filling the receive buffers.  size of rbuffc internal fifo insufficient. effects:  rxbuff interrupt (if buffien = 1 in chapter 5.0 , rslp channel configuration register).  data received during an over flow condition is discarded.
28560-DSH-001-B mindspeed technologies? 7 - 17 advance information cx28560 data sheet basic operations  data in the internal fifo is transfer red to the host, the receive fragment header of the last fragment is set as eom = 1, error = buff.  if errien is set in chapter 5.0 , rbuffc configuration register and chapter 5.0 , tbuffc configuration register, an rxerr interrupt is generated, indicating an rxbuff overflow.  when the overflow condition ends (i.e., space becomes available in the channel fifo), rslp automatically restarts data processing. however, rslp ignores all time slots until reaching the time slot marked ?first.?  rbuffc is not affected and continue s shared memory buffer processing. channel-level recovery actions:  if possible, increase internal fifo size assigned to this channel. for this action, all channel must first be deactivated.  notice that channel react ivation is not required. 7.3.5.2 receive change of frame alignment (cofa) same as hdlc mode. reason:  signal failure, glitch, or realignmen t caused by the physical interface sourcing the rsync or tstb inpu t signal. effects:  causes serial interface to enter co fa condition until the rsync/tstb pulse is followed by at least the assigned number of time slots for this port, without another unexpected rsync/tstb pulse.  current message processing is ended for every active channel on this port. all data received prior to the cofa condition is transferred to the host, and the receive fragment header is written w ith error = cofa. the only exception to this description happens when the cofa condition is detected within the first few bytes after channel activation or after the channel suffered an overflow or another cofa, as described in this section, short cofa (sht cofa).  receive cofa interrupt (if cofaien = 1 in chapter 5.0 , rsiu port configuration register). when the cofa condition ends, rslp restarts data processing automatically, however all time slots are ignored until the time slot marked ?first?.  rbuffc is not affected and continue s to transfer data to the host. channel-level recovery actions:  none required. 7.3.5.3 out of frame (oof) same as hdlc mode. reason:  roof input pin is asserted (high) because the attached physical layer device is unable to recover a valid, framed signal.
7-18 mindspeed technologies? 28560-DSH-001-B advance information basic operations cx28560 data sheet effects:  oof interrupt (if oofien = 1 and oofabt = 1 in chapter 5.0 , rsiu port configuration register).  if bit field oofabt = 0, rslp and rbuffc continue as if there are no errors and transfer received data to the host.  if bit field oofabt = 1, all incoming data is replaced by all 1s (0xff) data sequence. normal data processing re sumes when the roof input pin is deasserted (low), indicating the oof condition has ended.  rbuffc is not affected and continue s to transfer data to the host. channel-level recovery actions:  none required. 7.3.5.4 short cofa (sht cofa) a short cofa interrupt is generated for any transparent mode message whose reception is ended due to a cofa error an d for which no data was transferred from rslp to rbuffc or to the host. in this ca se, no other indication is provided for this errored message. note: only transparent mode cofa creates such a scenario. the exact scenario is as follows: a cofa condition happens within the next few bytes after an abnormal message termination (i.e., a prior cofa or overflow error) or after a channel activation. reason:  signal failure, glitch or realignment cau sed by the physical interface sourcing the rsync or tstb input signal. effects:  rxsht interrupt (if idleien = 1 in chapter 5.0 , rslp channel configuration register).  rslp restarts channel operation as soon as the cofa condition is recovered and the channel reaches its first assigned time slot.  rbuffc is not affected and continue s to transfer data to the host. channel-level recovery actions:  none required.
28560-DSH-001-B mindspeed technologies? 8 - 1 advance information 8.0 electrical and mechanical specification 8.1 electrical and environmental specifications 8.1.1 absolute maximum ratings stressing the device para meters beyond absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those listed in the operational sections of this specificatio n is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 8-1. absolute maximum ratings parameter symbol value unit minimum maximum core power supply v dd ?0.5 2.5 v i/o power supply v ddo ?0.5 4.6 v continuous power dissipation p d ??mw constant voltage on any signal pin v i ?1.0 v dd + 0.5 ? constant current on any signal pin i i ?10 10 ma transient current on any signal pin latchup (@25 c) ?300 300 ma transient current on any signal pin latchup (@125 c) ?150 150 ma transient voltage on any pin esd (hbm) ?2500 2500 v transient voltage on any pin esd (cdm) ?700 700 v operating junction temperature t j ?40 125 c storage temperature t s ?55 125 c
8-2 mindspeed technologies? 28560-DSH-001-B advance information electrical and mechan ical specification cx28560 data sheet 8.1.2 recommended operating conditions 8.1.3 electrical characteristics table 8-2. recommended 3.3 v operating conditions parameter symbol value unit minimum maximum power supply v dd 1.7 1.9 v i/o power supply v ddo 3.135 3.465 v ambient operating temperature kpf epf t ac 0 ?40 +70 +85 c c high-level input voltage v ih (1) 2.0 v ddo +0.5 v low-level input voltage v il (1) 00.8v high-level output current source i oh 200 400 a low level output current sink i ol 24ma output capacitive loading pci and line interfaces c ld 30 85 pf output capacitive loa ding pos-phy interface c ldpos 10 30 pf note(s): note(s): (1) (1) apply to all pins, except the pci interface, which is defined in table 8-4 . table 8-3. dc characteristics for 3.3 v operation parameter symbol value units high-level output voltage v oh 2.4 v low-level output voltage v ol 0.4 v input leakage current i l ?10 to 10 a three-state leakage current i oz ?10 to 10 a resistive pullup current i pr 20 to 100 a supply current i dd + i ddo 1000 + 340 ma
28560-DSH-001-B mindspeed technologies? 8 - 3 advance information cx28560 data sheet electrical and mech anical specification 8.2 timing and switching specifications 8.2.1 overview this section defines the timing and switching characteristics of cx28560. the major subsystems include the host interface, the expansion bus interface, the pos-phy interface and the serial interface. the host interface is peripheral component interface (pci) compliant. for othe r references to pci, see the pci local bus specification , revision 2.2, december 18, 1998. the pos-phy interface is compliant to the frame-based atm interface (level 3). for other references see atm forum technical committee document af-phy-0143.000, march 2000. the expansion bus and serial bus interfaces are similar to the host interface timing characteristics; the differences and specific characteristics commo n to either interface are further defined. 8.2.2 host interface (pci) timing and switching characteristics reference the pci local bus specification, revision 2.2 , december 18, 1998 for information the following:  indeterminate inputs and metastability  power requirements, se quencing, and decoupling  pci dc specifications  pci ac specifications pci v/i curves  maximum ac ratings and device protection table 8-4. pci interface dc specifications symbol parameter condition min max units v cc supply voltage ? 3 3.6 v v ih input high voltage ? 0.5 v ddo v ddo + 0.5 v v il input low voltage ? ?0.5 0.3 v ddo v i il input leakage current (1) 0 < v in < v cc ?+/-10 a v oh output high voltage i out = ?500 a 0.9 v ddo ?v v ol output low voltage (2) i out = 1500 a ? 0.1 v ddo v c out /c in /c io output, input, and i/o pin capacitance ? ? 10 pf c clk pclk pin capacitance ? 5 12 pf c idsel idsel pin capacitance (3) ??8pf l pin pin inductance ? ? 20 nh note(s): (1) input leakage currents include hi-z output leakage for all bi directional buffers with three-state outputs. (2) signals without pullup resistors must have 3 ma low output cu rrent. signals requiring pullup must have 6 ma; the latter include frame*, trdy*, irdy*, de vsel*, stop*, serr*, and perr*. (3) lower capacitance on this input-only pin a llows for non-resistive coupling to ad[xx].
8-4 mindspeed technologies? 28560-DSH-001-B advance information electrical and mechan ical specification cx28560 data sheet table 8-5. pci clock (pclk) waveform parameters, 3.3 v clock symbol parameter min 33 mhz max 33 mhz units t cyc clock cycle time (1) 30 infinite ns t high clock high time 11 ? ns t low clock low time 11 ? ns ? clock slew rate (2) 14v/ns v ptp peak-to-peak voltage 0.4 v cc ?v note(s): (1) cx28560 works with any clock frequency between dc and 33 mh z, nominally. the clock freque ncy may be changed at any time during operation of the system as long as clock edges remain monotonic, and minimum cy cle and high and low times are not violated. the clock may onl y be stopped in a low state. (2) rise and fall times are specified in terms of the edge rate me asured in v/ns. this slew rate must be met across the minimum peak-to-peak portion of the clock waveform. figure 8-1. pci clock (pclk) waveform, 3.3 v clock 500031a_001 0.6 0.5 0.4 0.3 v cc v cc v cc v cc v cc v ptp t low t cyc t high (min) 0.2 table 8-6. pci reset parameters symbol parameter min max units t rst reset active time after power stable 1 ? ms t rst_clk reset active time after clock stable 100 ? s t rst-off reset active to float delay ? 40 ns
28560-DSH-001-B mindspeed technologies? 8 - 5 advance information cx28560 data sheet electrical and mech anical specification table 8-7. pci input/output timing parameters symbol parameter min 33 mhz max 33 mhz units t val pclk to signal valid delay?bused signal ( 1, 2) 1.6 11 ns t val (ptp) pclk to signal valid delay?point to point ( 1, 2) 1.6 12 ns t on float to active delay (3) 2?ns t off active to float delay (3) ?28ns t ds input setup time to clock?bused signal (2) 7?ns t su (ptp) input setup time to clock?point to point (2) 10, 12 ? ns t dh input hold time from clock 0 ? ns note(s): (1) minimum and maximum times are evaluated at 50 pf equivalent load. actual test ca pacitance may vary, a nd results should be correlated to these specifications. (2) req* and gnt* are the only point-to-point signals, and have di fferent output valid delay and i nput setup times than do bused signals. gnt* has a setup of 10 ns; re q* has a setup of 12 ns for 33 mhz. (3) for purposes of active /float timing measurements, the hi-z or off state is defined to be when the total current delivered throu gh the component pin is less than or equal to the leakage current specification at 50 pf equivalent load.
8-6 mindspeed technologies? 28560-DSH-001-B advance information electrical and mechan ical specification cx28560 data sheet table 8-8. pci i/o measure conditions symbol parameter value unit v th voltage threshold high (1) 0.6 v ddo v v tl voltage threshold low (1) 0.2 v ddo v v trise voltage rise point 0.285 v ddo v v tfall voltage fall point 0.615 v ddo v v test voltage test point 0.4 v ddo v v max maximum peak-to-peak ( 2) 0.4 v ddo v ? input signal edge rate 1 v/ns note(s): (1) the input test is done with 0.1 v dd of overdrive (over v ih and v il ). timing parameters must be me t with no more overdrive than this. production testing can use different voltage values, but must correlate results back to these parameters. (2) v max specifies the maximum peak-to-peak vo ltage waveform allowed for measuring input timing. producti on testing can use different voltage values, but must correlate results back to these parameters. figure 8-2. pci output timing waveform 500031a_002 t off t on output delay pclk three-state output v tl v th v test t val v test (3.3 v signaling) output current leakage current <
28560-DSH-001-B mindspeed technologies? 8 - 7 advance information cx28560 data sheet electrical and mech anical specification 8.2.3 data interface (pos-phy) timi ng and switching characteristics all ac timing is from the perspective of the cx28560. figure 8-3. pci input timing waveform 500031a_003 clk input v tl t dh t ds v max v test v test v th inputs valid v th v tl table 8-9. transmit interface timing symbol description min max units ? tfclk frequency (1) ? 104 mhz ?tfclk duty cycle 40 60 % tstenb tenb setup time to tfclk 2 ? ns thtenb tenb hold time to tfclk 0.5 ? ns tstdat tdat[15:0] setup time to tfclk 2 ? ns thtdat tdat[15:0] hold time to tfclk 0.5 ? ns tstprty tprty setup time to tfclk 2 ? ns thtprty tprty hold time to tfclk 0.5 ? ns tstsop tsop setup time to tfclk 2 ? ns thtsop tsop hold time to tfclk 0.5 ? ns tsteop teop setup time to tfclk 2 ? ns thteop teop hold time to tfclk 0.5 ? ns tstmod tmod setup time to tfclk 2 ? ns thtmod tmod hold time to tfclk 0.5 ? ns tsterr terr setup time to tfclk 2 ? ns thterr terr hold time to tfclk 0.5 ? ns tpptpa tfclk high to ptpa valid 1.5 6 ns note(s): (1) recommended: 100 mhz
8-8 mindspeed technologies? 28560-DSH-001-B advance information electrical and mechan ical specification cx28560 data sheet figure 8-4. transmit physical timing note(s): 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is th e time in nanoseconds from the 1.4 volt point of the clock to the 1. 4 volt point of the input. 3. output propagation delay time is the ti me in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 4. maximum output propagation delays are me asured with a 30 pf load on the outputs.
28560-DSH-001-B mindspeed technologies? 8 - 9 advance information cx28560 data sheet electrical and mech anical specification table 8-10. receive interface timing symbol description min max units ? rfclk/frfclk fr equency ? 104 mhz ? rfclk/frfclk duty cycle 40 60 % tsrenb renb/frenb set-up time to rfclk/frfclk 2 ? ns threnb renb/frenb hold ti me to rfclk/frfclk 0.5 ? ns tprdat rfclk/frfclk high to rdat/frdat valid 1.5 6 ns tprprty rfclk/frfclk high to rprty/frprty valid 1.5 6 ns tprsop rfclk/frfclk high to rsop/frsop valid 1.5 6 ns tpreop rfclk/frfclk high to reop/freop valid 1.5 6 ns tprmod rfclk high to rmod valid 1.5 6 ns tprval rfclk/frfclk high to rval/frval valid 1.5 6 ns (1) recommended: 100 mhz
8-10 mindspeed technologies? 28560-DSH-001-B advance information electrical and mechan ical specification cx28560 data sheet figure 8-5. receive physical timing note(s): 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is th e time in nanoseconds from the 1.4 volt point of the clock to the 1. 4 volt point of the input. 3. output propagation delay time is the ti me in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 4. maximum output propagation delays are me asured with a 30 pf load on the outputs.
28560-DSH-001-B mindspeed technologies? 8 - 11 advance information cx28560 data sheet electrical and mech anical specification 8.2.4 expansion bus (ebus) timi ng and switching characteristics the ebus timing is derived directly from the pci clock (pclk) input into cx28560. the ebus clock can have the same frequency as the pci clock, or it can have half the frequency of the pci clock. table 8-11. ebus reset parameters symbol parameter min max units t off active to inactive delay (1) ?28 ns note(s): (1) for purposes of active/float timi ng measurements, the hi-z or off state is defined to be when th e total current delivered throu gh the component pin is less than or equa l to the leakage current specification. figure 8-6. ebus reset active to inactive delay note(s): the ebus reset is dependent on the pr st* (pci reset) signal being asserted low. pci reset ebus three-state output t off ebus input reset period three-state input ignored table 8-12. ebus input/output timing parameters symbol parameter min max units t val eclk to signal valid delay ( 1) ?0.5 4.5 ns t on float to active delay (2) 2?ns t off active to float delay (2) ?28 ns t ds input setup time to clock 18 ? ns t dh input hold time from clock 1 ? ns note(s): (1) minimum and maximum times are evaluated at 40 pf equivalent load. actu al test capacitance may vary, and results should be correlated to these specifications. (2) for purposes of active/float timi ng measurements, the hi-z or off state is defined to be when th e total current delivered throu gh the component pin is less than or equal to the leakage current specification at 40 pf equivalent load.
8-12 mindspeed technologies? 28560-DSH-001-B advance information electrical and mechan ical specification cx28560 data sheet table 8-13. ebus input/output measure conditions symbol parameter value units v th voltage threshold high (1) 0.6 v ddo v v tl voltage threshold low (1) 0.2 v ddo v v test voltage test point 0.4 v ddo v v max maximum peak-to-peak ( 2) 0.4 v ddo v ? input signal slew rate 1.5 v/ns note(s): (1) the input test for the 3.3 v en vironment is done with 0.1*v ddo of overdrive. timing paramete rs must be met with no more overdrive than this. production testing may us e different voltage values, but must corre late results back to these parameters. (2) v max specifies the maximum peak-to-peak vo ltage waveform allowed for measuring input timing. producti on testing may use different voltage values, but must correlate results back to these parameters. figure 8-7. ebus output timing waveform figure 8-8. ebus input timing waveform eclk output delay v th v tl v test v test t val 500031a_06 eclk input v th v tl v test v test v test v max v th v tl t ds t dh 500031a_07
28560-DSH-001-B mindspeed technologies? 8 - 13 advance information cx28560 data sheet electrical and mech anical specification 8.2.5 ebus arbitration timing specification figure 8-9. ebus write/read cycle, intel-style note(s): 1. hlda assertion depends on the external bus arbiter. while hold and hlda ar e both deasserted, cx28560 places shared ebus signals in high impedance (thr ee-state, shown as dashed lines). 2. one eclk cycle after hlda assertion, cx28560 outputs valid command bus signals: ebe, ale, rd*, and wr*. 3. two eclk cycles after hl da assertion, cx 28560 outputs valid ead address signals. 4. ale assertion occurs 3 eclk cycles after hold and hlda are both asserted . alapse inserts a vari able number of eclk cycles to extend ale high pulse width and ead address interval. 5. ead address remains valid for one eclk cycle after ale falling edge. during a write transaction, cx28560 outputs valid ead write data one eclk prior to wr* assertion. during a read transa ction, ead data lines are inputs. 6. elapse inserts a variable number of eclk cycles to extend rd*/wr* low pulse width and ead data intervals. read data inputs are sampled on eclk rising edge coincident with rd* deassertion. 7. ead write data and ebe byte enables remain va lid for one eclk cycle af ter rd*/wr* deassertion. 8. one eclk after rd* or wr* deassertion, hold is deasserted and the bus is pa rked (command bus de asserted, ead three- state). the bus parked state ends when hlda is deasserted. 9. command bus is unparked (thr ee-stated) one eclk after hl da deassertion; two different unpark phases are shown, indicating the dependence on hlda deassertion. if hlda remained asserted until the next bus reque st, then command bus remains parked until one eclk cycle followi ng the next hold assertion. caution: whenever hlda is deasserted, all shared ebus signals are forced to three-state after one eclk cycle, regardless of whether the ebus transaction was completed. cx28560 does not reissue or repeat such an aborted transaction. 10. blapse inserts a variable number of eclk cycles to extend hold deassertion interval until the next bus request. alapse - 0 elapse - 0 blapse - 0 eclk hold hlda see notes wr*(write) rd*(read) rd*(write) ebe[3:0] ead[31:d] ale wr*(read) 1 2 3 4 5 6 78 10 9 address data byte enables from pci data phase
8-14 mindspeed technologies? 28560-DSH-001-B advance information electrical and mechan ical specification cx28560 data sheet figure 8-10. ebus write/read cycle, motorola-style note(s): 1. bg* assertion depends on the external bus arbiter. while bg* and br* are both deasserted , cx28560 places shared ebus signals in high impedance (three -state, shown as dashed lines). 2. one eclk cycle after bg* asserti on, cx28560 outputs valid command bus signals: ebe, as*, r/wr*, and ds*. 3. two eclk cycles after bg* assertion, cx28560 outputs valid ead address signals. bgack* assertion occurs three eclk cycles after bg* and br* are both asserted. 4. alapse inserts a variable number of eclk cycles to extend as* high pulse width and ead address interval. 5. ead address remains valid for one eclk cycle after as* falling edge. during a write transaction, cx28560 asserts r/wr* and outputs valid ead write data one eclk prior to ds* assert ion. during a read transacti on, ead data lines are inputs. 6. elapse inserts a variable number of eclk cycles to extend ds* low pulse width an d ead data interval. read data inputs are sampled on eclk rising edge co incident with ds* deassertion. 7. ead write data, ebe, r/wr* and as* si gnals remain valid for one eclk cycle after bgack* and ds* are deasserted. 8. one eclk cycle after bgack* deassertion, the br* output is deasserted and the bus is parked (command bus deasserted, ead three-state). the bus parked state ends when the external bus arbiter deasserts bg*. 9. command bus is unparked (thr ee-stated) one eclk after bg* deassertion; tw o different unpark phases are shown, indicating the dependence on bg * deassertion. if bg* remain ed asserted until the next bus request, then command bus remains parked until one eclk following the next br* assert ion. caution: whenever bg* is deasserted, all shared ebus signals are forced to three-state after one eclk cycle, regardless of whether the ebus transaction was completed. cx28560 does not reissue or repeat such an aborted transaction. 10. blapse inserts a variable number of eclk cycles to ex tend br* deassertion interval until the next bus request. alapse - 0 elapse - 0 blapse - 0 eclk see notes r/wr*(read) r/wr*(write) ebe[3:0]* ead[31:0] as* 1 2 3 4 5 6 78 10 9 address data byte enables from pci data phase ds* bgack* bg* br*
28560-DSH-001-B mindspeed technologies? 8 - 15 advance information cx28560 data sheet electrical and mech anical specification 8.2.6 serial interface timing a nd switching characteristics table 8-14. serial interface clock (rclk, tclk) parameters symbol parameter min max units f c clock frequency dc 52 mhz t r clock rise time for fc 10 mhz ? 20 ns t r clock rise time for fc > 10 mhz ? 3 ns t f clock fall time for fc 10 mhz ? 20 ns ? clock fall time for fc > 10 mhz ? 3 ns ? clock duty cycle 40 60 % figure 8-11. serial interface clock (rclk,tclk) waveform t r 500031a_017 t f 1/f c rclk, tclk table 8-15. serial interface input/output timing parameters symbol parameter min max units clock to signal valid delay for fc 10 mhz 2 30 ns clock to signal valid delay for fc > 10 mhz 2 8 ns data setup time for fc 10 mhz 15 ? ns data setup time for fc > 10 mhz 2 ? ns data hold time for fc 10 mhz 15 ? ns data hold time for fc > 10 mhz 3 ? ns note(s): 1. parameters were characterized with c load = 70 pf 2. output delay 3. input signals t 2 val t 3 ds t 3 dh
8-16 mindspeed technologies? 28560-DSH-001-B advance information electrical and mechan ical specification cx28560 data sheet table 8-16. serial interface input/output measure conditions symbol parameter value units v th voltage threshold high (1) 0.6 v ddo v v tl voltage threshold low (1) 0.2 v ddo v v test voltage test point 0.4 v ddo v v max maximum peak-to-peak ( 2) 0.4 v ddo v ? input signal slew rate 1.5 v/ns c ld maximum load capaci tance?output and i/0 70 pf note(s): (1) the input test for the 3.3 v en vironment is done with 0.1*v ddo of overdrive. timing paramete rs must be met with no more overdrive than this. production testing may us e different voltage values, but must corre late results back to these parameters. (2) v max specifies the maximum peak-to-peak vo ltage waveform allowed for measuring input timing. producti on testing may use different voltage values, but must correlate results back to these parameters. figure 8-12. serial interface data input waveform rclk rdat (rising) rdat (falling) v th v tl v th t ds t ds t dh t dh v tl v test v test v test v test v test v max v max v test t val t val v th v tl 500031a_011
28560-DSH-001-B mindspeed technologies? 8 - 17 advance information cx28560 data sheet electrical and mech anical specification figure 8-13. serial interface data delay output waveform 500031a_012 v test v test v test v test v test v test v max v max t val t val v th v tl v th v tl v th v tl tclk tdat (rising) tdat (falling)
8-18 mindspeed technologies? 28560-DSH-001-B advance information electrical and mechan ical specification cx28560 data sheet figure 8-14. transmit and receive t1 mode note(s): 1. t1 mode employs 24 time slots (0?23) wi th 8 bits per time slot (0?7) and 1 fr ame-bit every 193 clock periods. one frame of 193 bits occurs every 125 s (1.544 mhz). 2. rsync and tsync must be assert ed for a minimum of 1 clk period. 3. cx28560 can be configured to sample rsync, tsync, rdat, and tdat on eith er a rising or falling clock edge independently of an y other signal samp ling configuration. 4. relationships between the vari ous configurations of active edges for the synchronization si gnal and the data signal are shown using a common clock signal for re ceive and transmit operations. note the relationship between the frame bit (within rdat, tdat) and the frame sync hronization signal (e.g., rsync, tsync). 5. all received signals (e.g., rsync, rdat, tsync) are ?sampl ed? in on the specified clock e dge (e.g., rclk , tclk). all transmit data signals (tdat) are latched on the spec ified clock edge. 6. in configuration (a), synchroniza tion and data signals ar e sampled/latched on a rising clock edge. 7. in configuration (b), synchronization si gnal is sampled on a rising clock edge a nd the data signal is sampled/latched on a falling clock edge. 8. in configuration (c), synchronization si gnal is sampled on a falling clock edge and the data signal is sampled/latched on a rising clock edge. 9. in configuration (d), synchroni zation and data signals are sampled /latched on a falling clock edge. rclk tclk rsync-rise(a) rsync-rise(b) rdat-fall(b) rdat-fall(d) rsync-fall(c) rsync-fall(d) rdata-rise(a) rdata-rise(c) tsync-rise(a) tsync-rise(b) tdata-fall(b) tdata-fall(d) tsync-fall(c) tsync-fall(d) tdat-rise(a) tdat-rise(c)
28560-DSH-001-B mindspeed technologies? 8 - 19 advance information cx28560 data sheet electrical and mech anical specification figure 8-15. transmit and receive channelized non-t1 (i.e., n x 64) mode legend: m = n 8 bits, where m = number of time slots. note(s): 1. e1 mode employs 32 time slots (0?31) with 8 bits per time slot (0?7) and 256 bi ts per frame and one frame every 125 s (2.048 mhz). 2. 2xe1 mode employs 64 time slots (0?63) with 8 bits per time slot (0?7) and 512 bits per frame an d one frame every 125 s (4.096 mhz). 3. 4xe1 mode employs 128 time sl ots (0?127) with 8 bits per ti me slot (0?7) and 1024 bits per frame and one frame every 125 s (8.192 mhz). 4. rsync and tsync must be assert ed for a minimum of 1 clk period. 5. cx28560 can be configured to sample rsync, tsync, rdat, and tdat on eith er a rising or falling clock edge independently of an y other signal samp ling configuration. 6. relationships between the vari ous configurations of active edges for the synchronization si gnal and the data signal are shown using a common clock signal for re ceive and transmit operations. note the relationship between the frame bit (within rdat, tdat) and the frame sync hronization signal (e.g . rsync, tsync). 7. all received signals (e.g., rsync, rdat, tsync) are samp led in on the specif ied clock edge (e.g. rclk, tclk). all transmit data signals (tdat) are latched on the spec ified clock edge. 8. in configuration (a), synchroniza tion and data signals ar e sampled/latched on a rising clock edge. 9. in configuration (b), synchronization si gnal is sampled on a rising clock edge a nd the data signal is sampled/latched on a falling clock edge. 10. in configuration (c), synchronization si gnal is sampled on a falling clock edge and the data signal is sampled/latched on a rising clock edge. 11. in configuration (d), synchroni zation and data signals are sampled /latched on a falling clock edge. 12. in tsbus mode, the timing is identical to that in non-t1 mode. in order to convert the above diag ram to tsbus mode, the names of the signals should be replaced as described in chapter 1.0 , pin descriptions. the additi onal 2 pins in the first 12 ports (rgsync and tgsync) behave in an identical manner to rdat and tdat respectively. rclk tclk rsync-rise(b) rdat-fall(b) rdat-fall(d) rsync-fall(c) rsync-fall(d) rdata-rise(c) tsync-rise(a) tsync-rise(b) tdata-fall(b) tdata-fall(d) tsync-fall(c) tsync-fall(d) tdat-rise(a) tdat-rise(c) rsync-rise(a) rdata-rise(a)
8-20 mindspeed technologies? 28560-DSH-001-B advance information electrical and mechan ical specification cx28560 data sheet 8.2.7 test and diagnos tic interface timing table 8-17. test and diagnostic interface timing requirements symbol parameter minimum maximum units 1 tck pulse-width high 80 ? ns 2 tck pulse-width low 80 ? ns 3 tms, tdi setup prior to tck rising edge (1) 15 ? ns 4 tms, tdi hold after tck high (1) 20 ? ns note(s): (1) also applies to functional inputs for sample/preload and extest instructions. table 8-18. test and diagnostic interface switching characteristics symbol parameter minimum maximum units 5 tdo hold after tck falling edge 0 ? ns 6 tdo delay after tck low ? 50 ns 7 tdo enable (low z) after tck falling edge 2 15 ns 8 tdo disable (high z) after tck low ? 25 ns note(s): also applies to functional ou tputs for the extest instruction. figure 8-16. jtag interface timing note(s): please refer to tables 8-14 and 8-15 for numerical sy mbol reference. tdo tck 3 4 2 6 5 1 7 8 tdi tms
28560-DSH-001-B mindspeed technologies? 8 - 21 advance information cx28560 data sheet electrical and mech anical specification 8.3 package thermal specification theta ja for: 0 lfpm: 10.0 c/w 100 lfpm: 8.8 c/w 200 lfpm: 8.3 c/w 400 lfpm: 7.7 c/w 600 lfpm: 7.1 c/w
8-22 mindspeed technologies? 28560-DSH-001-B advance information electrical and mechan ical specification cx28560 data sheet 8.4 mechanical specification figure 8-17. package diagram 101302_028 a a1 d d1 e e1 b c m n aaa ccc e p g ref. 1.20 0.40 39.8 39.8 0.05 0.80 0.15 0.35 1.60 0.60 40.2 40.2 0.75 1.00 0.15 0.15 1.40 0.50 40 38.0 bsc. 40 38.0 bsc. 0.625 0.90 39 680 1.00 typ. min. max. nom. dimensional references note(s): 1. all dimensions are in millimeters. 2. "e" represents the basic solder ball grid pitch. 3. "m" represents the basic solder ball matrix size. and symbol "n" is the maximum allowable number of balls after depopulating. "b" is measured at the maximum solder ball diameter after reflow parallel to primary datum . dimension "aaa" ismeasured parallel to primary datum . primary datum and seating plane are defined by the sherical crowns of the solder balls. 7. package surface shall be black oxide. 8. cavity depth c1 various with die thickness. 9. substrate material base is copper. bilateral tolerance zone is applied to each side of package body. 45 deg. 0.35 mm chamfer coner and white dot for pin 1 identification. heatspreader thickness dimension is set by die thickness. 13. dimensioning and tolerancing per asme y14.5m 1994. ? a ? ? b ? ? c ? ? c ? ? c ? ? c ? 00.30 c a mmbm 00.30 c m (4 pls, 45? 0.35 mm chamfer) 0.10 10 11 4 ccc c aaa c c 6 5 4. 5. 6. 10. 11. 12. a1 a p d e e1 e g g b e d1 bottom view top view detail b detail a side view detail b detail a corner a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 c e g j b d f h k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al am an ap ar at au av aw
28560-DSH-001-B mindspeed technologies? 9 - 1 advance information 9.0 package description
package description cx28560 data sheet hdlc controller 9-2 mindspeed technologies? 28560-DSH-001-B advance information table 9-1. pin list for 28560 hdlc controller?alphabetic order (1 of 2) ball reference a1 gnd a2 gnd a3 gnd a4 gnd a36 gnd a37 gnd a38 gnd a39 gnd b1 gnd b2 gnd b3 gnd b4 gnd b10 gnd b16 gnd b22 gnd b28 gnd b34 gnd b36 gnd b37 gnd b38 gnd b39 gnd c1 gnd c2 gnd c3 gnd c4 gnd c36 gnd c37 gnd c38 gnd c39 gnd d1 gnd d2 gnd d3 gnd d4 gnd d36 gnd d37 gnd d38 gnd d39 gnd e1 gnd e5 gnd e8 gnd e10 gnd e12 gnd e14 gnd e16 gnd e18 gnd e20 gnd e22 gnd e24 gnd e26 gnd e28 gnd e30 gnd e32 gnd e34 gnd e39 gnd f3 gnd h2 gnd h5 gnd h35 gnd h38 gnd k5 gnd k35 gnd m2 gnd m5 gnd m35 gnd m38 gnd p5 gnd p35 gnd t2 gnd t5 gnd t35 gnd t38 gnd v5 gnd ball reference v35 gnd y2 gnd y5 gnd y35 gnd y38 gnd ab5 gnd ab35 gnd ad2 gnd ad5 gnd ad35 gnd ad38 gnd af5 gnd af35 gnd ah2 gnd ah5 gnd ah35 gnd ah38 gnd ak3 gnd ak5 gnd ak35 gnd al2 gnd am1 gnd am3 gnd am5 gnd am35 gnd am38 gnd an4 gnd ap2 gnd ar2 gnd ar5 gnd ar8 gnd ar10 gnd ar12 gnd ar14 gnd ar16 gnd ar18 gnd ball reference
cx28560 data sheet package description hdlc controller 28560-DSH-001-B mindspeed technologies? 9-3 advance information ar20 gnd ar22 gnd ar24 gnd ar26 gnd ar28 gnd ar30 gnd ar32 gnd ar35 gnd at1 gnd at2 gnd at3 gnd at5 gnd at8 gnd at14 gnd at35 gnd at36 gnd at37 gnd at38 gnd at39 gnd au1 gnd au2 gnd au3 gnd au4 gnd au6 gnd au9 gnd au12 gnd au36 gnd au37 gnd au38 gnd au39 gnd av1 gnd av2 gnd av3 gnd av4 gnd av7 gnd ball reference av10 gnd av15 gnd av19 gnd av23 gnd av27 gnd av31 gnd av34 gnd av36 gnd av37 gnd av38 gnd av39 gnd aw1 gnd aw2 gnd aw3 gnd aw4 gnd aw5 gnd aw13 gnd aw34 gnd aw35 gnd aw36 gnd aw37 gnd aw38 gnd aw39 gnd ball reference table 9-1. pin list for 28560 hdlc controller?alphabetic order (2 of 2)
package description cx28560 data sheet hdlc controller 9-4 mindspeed technologies? 28560-DSH-001-B advance information table 9-2. bga assignments for power (vddc, vddo and vgg) ball supply type e6 vddc e7 vddc e11 vddc e15 vddc e19 vddc e23 vddc e27 vddc e31 vddc f35 vddc g35 vddc j5 vddc l35 vddc n5 vddc r35 vddc u5 vddc w35 vddc aa5 vddc ac35 vddc ae5 vddc ag35 vddc aj5 vddc al35 vddc an5 vddc ap5 vddc ar9 vddc ar13 vddc ar17 vddc ar21 vddc ar25 vddc ar29 vddc ar33 vddc ar34 vddc e9 vddo e13 vddo e17 vddo e21 vddo e25 vddo e29 vddo e33 vddo f5 vddo g5 vddo j35 vddo l5 vddo n35 vddo r5 vddo u35 vddo w5 vddo aa35 vddo ac5 vddo ae35 vddo ag5 vddo aj35 vddo al5 vddo an35 vddo ap35 vddo ar6 vddo ar7 vddo ar11 vddo ar15 vddo ar19 vddo ar23 vddo ar27 vddo ar31 vddo at11 vddo e35 vgg au7 vgg ball supply type
cx28560 data sheet package description hdlc controller 28560-DSH-001-B mindspeed technologies? 9-5 advance information table 9-3. signals (1 of 7) pad# name package ball 3 tdat[17] f4 4 tsync[17]/tstuff[17] e2 5 tclk[17] e3 6 rclk[17] e4 9 roof[17]/cts[17]/tstb[17] a5 10 rsync[17]/rstuff[17] b5 11 rdat[17] c5 12 roof[16]/cts[16]/tstb[16] d5 13 tdat[16] a6 14 tsync[16]/tstuff[16] b6 15 tclk[16] c6 16 rclk[16] d6 19 rsync[16]/rstuff[16] a7 20 rdat[16] b7 21 roof[15]/cts[15]/tstb[15] c7 22 tdat[15] d7 23 tsync[15]/tstuff[15] a8 24 tclk[15] b8 27 rclk[15] c8 28 rsync[15]/rstuff[15] d8 29 rdat[15] a9 30 roof[14]/cts[14]/tstb[14] b9 31 tdat[14] c9 32 tsync[14]/tstuff[14] d9 33 tclk[14] a10 36 rclk[14] c10 37 rsync[14]/rstuff[14] d10 38 rdat[14] a11 39 roof[13]/cts[13]/tstb[13] b11 40 tdat[13] c11 41 tsync[13]/tstuff[13] d11 42 tclk[13] a12 43 rclk[13] b12 46 rsync[13]/rstuff[13] c12 47 rdat[13] d12 48 roof[12]/cts[12]/tstb[12] a13 49 tdat[12] b13 50 tsync[12]/tstuff[12] c13 51 tclk[12] d13 52 rclk[12] a14 53 rsync[12]/rstuff[12] b14 54 rdat[12] c14 57 roof[11]/cts[11]/tstb[11] d14 58 tdat[11] a15 59 tsync[11]/tstuff[11] b15 60 tclk[11] c15 61 rclk[11] d15 64 rdat[11] a16 65 tgsync[11] c16 66 rgsync[11] d16 67 rsync[11]/rstuff[11] a17 68 roof[10]/cts[10]/tstb[10] b17 69 tdat[10] c17 71 tsync[10]/tstuff[10] d17 72 tclk[10] a18 73 tgsync[10] b18 74 rgsync[10] c18 77 rsync[10]/rstuff[10] d18 78 rclk[10] a19 79 rdat[10] b19 80 roof[9]/cts[9]/tstb[9] c19 81 tdat[9] d19 82 tsync[9]/tstuff[9] a20 83 tgsync[9] b20 84 rgsync[9] c20 85 tclk[9] d20 pad# name package ball
package description cx28560 data sheet hdlc controller 9-6 mindspeed technologies? 28560-DSH-001-B advance information 86 rclk[9] a21 87 rsync[9]/rstuff[9] b21 88 rdat[9] c21 89 roof[8]/cts[8]/tstb[8] d21 90 tgsync[8] a22 93 rgsync[8] c22 94 tdat[8] d22 95 tsync[8]/tstuff[8] a23 96 tclk[8] b23 99 rclk[8] c23 100 rsync[8]/rstuff[8] d23 101 rdat[8] a24 102 tgsync[7] b24 103 rgsync[7] c24 104 roof[7]/cts[7]/tstb[7] d24 105 tdat[7] a25 106 tsync[7]/tstuff[7] b25 107 tclk[7] c25 110 rclk[7] d25 111 rsync[7]/rstuff[7] a26 112 rdat[7] b26 113 roof[6]/cts[6]/tstb[6] c26 115 tdat[6] d26 116 tsync[6]/tstuff[6] a27 117 tgsync[6] b27 118 rgsync[6] c27 119 tclk[6] d27 122 rclk[6] a28 123 rsync[6]/rstuff[6] c28 124 rdat[6] d28 125 roof[5]/cts[5]/tstb[5] a29 126 tdat[5] b29 129 tsync[5]/tstuff[5] c29 pad# name package ball 130 tclk[5] d29 131 tgsync[5] a30 132 rgsync[5] b30 133 rclk[5] c30 136 rsync[5]/rstuff[5] d30 137 rdat[5] a31 138 roof[4]/cts[4]/tstb[4] b31 139 tdat[4] c31 141 tsync[4]/tstuff[4] d31 142 tclk[4] a32 143 tgsync[4] b32 144 rgsync[4] c32 147 rclk[4] d32 148 rsync[4]/rstuff[4] a33 149 rdat[4] b33 150 roof[3]/cts[3]/tstb[3] c33 151 tdat[3] d33 154 tsync[3]/tstuff[3] a34 155 tclk[3] c34 156 tgsync[3] d34 157 rgsync[3] a35 160 rclk[3] b35 161 rsync[3]/rstuff[3] c35 162 rdat[3] d35 163 roof[2]/cts[2]/tstb[2] e38 164 tdat[2] e37 165 tsync[2]/tstuff[2] e36 169 tclk[2] f39 170 tgsync[2] f38 171 rgsync[2] f37 173 rclk[2] f36 176 rsync[2]/rstuff[2] g39 177 rdat[2] g38 pad# name package ball table 9-3. signals (2 of 7)
cx28560 data sheet package description hdlc controller 28560-DSH-001-B mindspeed technologies? 9-7 advance information 178 roof[1]/cts[1]/tstb[1] g37 181 tdat[1] g36 182 tsync[1]/tstuff[1] h39 185 tclk[1] h37 186 tgsync[1] h36 187 rgsync[1] j39 188 rclk[1] j38 189 rsync[1]/rstuff[1] j37 190 rdat[1] j36 193 roof[0]/cts[0]/tstb[0] k39 194 tdat[0] k38 195 tsync[0]/tstuff[0] k37 198 tclk[0] k36 199 tgsync[0] l39 200 rgsync[0] l38 201 rclk[0] l37 202 rsync[0]/rstuff[0] l36 203 rdat[0] m39 204 roof[24]/cts[24]/tstb[24] m37 205 tdat[24] m36 206 tsync[24]/tstuff[24] n39 207 tclk[24] n38 210 rclk[24] n37 211 rsync[24]/rstuff[24] n36 214 rdat[24] p39 215 roof[25]/cts[25]/tstb[25] p38 216 tdat[25] p37 217 tsync[25]/tstuff[25] p36 218 rclk[25] r39 221 tclk[25] r38 222 rsync[25]/rstuff[25] r37 223 rdat[25] r36 224 roof[26]/cts[26]/tstb[26] t39 pad# name package ball 225 tdat[26] t37 227 tclk[26] t36 228 tsync[26]/tstuff[26] u39 229 rclk[26] u38 232 rsync[26]/rstuff[26] u37 233 rdat[26] u36 234 roof[27]/cts[27]/tstb[27] v39 235 tdat[27] v38 236 tsync[27]/tstuff[27] v37 237 tclk[27] v36 238 rclk[27] w39 239 rsync[27]/rstuff[27] w38 240 rdat[27] w37 243 roof[28]/cts[28]/tstb[28] w36 244 tdat[28] y39 245 tsync[28]/tstuff[28] y37 246 tclk[28] y36 247 rclk[28] aa39 248 rsync[28]/rstuff[28] aa38 249 rdat[28] aa37 250 roof[29]/cts[29]/tstb[29] aa36 251 tdat[29] ab39 252 tsync[29]/tstuff[29] ab38 255 tclk[29] ab37 256 rclk[29] ab36 257 rsync[29]/rstuff[29] ac39 258 rdat[29] ac38 259 roof[30]/cts[30]/tstb[30] ac37 260 tdat[30] ac36 263 tsync[30]/tstuff[30] ad39 264 tclk[30] ad37 265 rclk[30] ad36 266 rsync[30]/rstuff[30] ae39 pad# name package ball table 9-3. signals (3 of 7)
package description cx28560 data sheet hdlc controller 9-8 mindspeed technologies? 28560-DSH-001-B advance information 267 rdat[30] ae38 268 roof[31]/cts[31]/tstb[31] ae37 269 tdat[31] ae36 270 tsync[31]/tstuff[31] af39 271 tclk[31] af38 272 rclk[31] af37 273 rsync[31]/rstuff[31] af36 274 rdat[31] ag39 276 frclav ag38 277 freop ag37 280 frsop ag36 281 frprty ah39 282 frdat[0] ah37 285 frdat[1] ah36 286 frdat[2] aj39 287 frdat[3] aj38 290 frdat[4] aj37 291 frdat[5] aj36 294 frdat[6] ak39 295 frdat[7] ak38 296 frenb ak37 297 frval ak36 298 frfclk al39 301 tdata[0] al38 302 tdata[1] al37 303 tdata[2] al36 304 tdata[3] am39 305 tdata[4] am37 306 tdata[5] am36 307 tdata[6] an39 308 tdata[7] an38 309 tdata[8] an37 312 tdata[9] an36 pad# name package ball 313 tdata[10] ap39 314 tdata[11] ap38 315 tdata[12] ap37 316 tdata[13] ap36 317 tdata[14] ar39 318 tdata[15] ar38 319 tdata[16] ar37 322 tdata[17] ar36 323 tdata[18] au35 324 tdata[19] av35 325 tdata[20] au34 326 tdata[21] at34 327 tdata[22] aw33 328 tdata[23] av33 332 tdata[24] au33 333 tdata[25] at33 334 tdata[26] aw32 335 tdata[27] av32 336 tdata[28] au32 337 tdata[29] at32 338 tdata[30] aw31 339 tdata[31] au31 342 ptpa at31 343 terr aw30 344 teop av30 345 tsop au30 346 tprty at30 349 tmod[0] aw29 350 tmod[1] av29 351 tenb au29 354 tfclk at29 355 tm[0] aw28 356 tm[1] av28 pad# name package ball table 9-3. signals (4 of 7)
cx28560 data sheet package description hdlc controller 28560-DSH-001-B mindspeed technologies? 9-9 advance information 357 tm[2] au28 359 tm[3] at28 360 ad[0] aw27 361 ad[1] au27 362 ad[2] at27 363 ad[3] aw26 366 ad[4] av26 367 ad[5] au26 368 cbe[0] at26 372 ad[6] av25 369 ad[7] aw25 373 ad[8] au25 375 ad[9] aw24 374 ad[10] at25 376 ad[11] av24 377 ad[12] au24 378 ad[13] at24 379 ad[14] aw23 382 ad[15] au23 383 cbe[1] at23 384 par aw22 385 serr av22 386 perr au22 387 stop at22 390 devsel aw21 391 trdy av21 394 irdy au21 395 frame at21 396 cbe[2] aw20 397 ad[16] av20 398 ad[17] au20 399 ad[18] at20 400 ad[19] aw19 pad# name package ball 403 ad[20] au19 404 ad[21] at19 405 ad[22] aw18 406 ad[23] av18 409 idsel au18 410 cbe[3] at18 411 ad[24] aw17 412 ad[25] av17 413 ad[26] au17 416 ad[27] at17 417 ad[28] aw16 418 ad[29] av16 419 ad[30] au16 420 ad[31] at16 421 req aw15 422 gnt au15 424 pclk at15 427 prst aw14 428 inta av14 431 onesec au14 434 rclav av13 435 reop au13 436 rsop at13 439 rprty aw12 440 rmod[0] av12 441 rmod[1] at12 444 rdata[0] aw11 445 rdata[1] av11 446 rdata[2] au11 449 rdata[3] aw10 450 rdata[4] au10 455 rdata[5] at10 456 rdata[6] aw9 pad# name package ball table 9-3. signals (5 of 7)
package description cx28560 data sheet hdlc controller 9-10 mindspeed technologies? 28560-DSH-001-B advance information 460 rdata[7] av9 461 rdata[8] at9 464 rdata[9] aw8 465 rdata[10] av8 470 rdata[11] au8 471 rdata[12] aw7 477 rdata[13] at7 478 rdata[14] aw6 481 rdata[15] av6 482 rdata[16] at6 485 rdata[17] av5 486 rdata[18] au5 489 renb at4 490 rval ar4 493 rdata[19] ar3 494 rdata[20] ar1 496 rfclk ap4 498 rdata[21] ap3 499 rdata[22] ap1 502 rdata[23] an3 503 rdata[24] an2 506 rdata[25] an1 507 rdata[26] am2 508 rdata[27] am4 511 rdata[28] al1 512 rdata[29] al3 515 rdata[30] al4 516 rdata[31] ak1 519 ead[0] ak2 520 ead[1] ak4 521 ead[2] aj1 522 ead[3] aj2 525 ead[4] aj3 pad# name package ball 526 ead[5] aj4 527 ead[6] ah1 528 ead[7] ah3 531 ead[8] ah4 532 ead[9] ag1 533 ead[10] ag2 536 ead[11] ag3 537 ead[12] ag4 538 ead[13] af1 539 ead[14] af2 542 ead[15] af3 543 ead[16] af4 544 ead[17] ae1 545 ead[18] ae2 546 ead[19] ae3 549 ead[20] ae4 550 ead[21] ad1 551 ead[22] ad3 554 ead[23] ad4 555 ead[24] ac1 558 ead[25] ac2 559 ead[26] ac3 560 ead[27] ac4 561 ead[28] ab1 564 ead[29] ab2 565 ead[30] ab3 566 ead[31] ab4 567 wr (r/wr) aa1 568 rd (ds) aa2 571 eclk aa3 572 ale (as) aa4 573 hold (br) y1 574 hlda (bg*) y3 pad# name package ball table 9-3. signals (6 of 7)
cx28560 data sheet package description hdlc controller 28560-DSH-001-B mindspeed technologies? 9-11 advance information 575 bgack y4 578 ebe[3] w1 579 ebe[2] w2 582 ebe[1] w3 583 ebe[0] w4 586 tdi v1 587 tdo v2 588 tms v3 589 tck v4 590 trst u1 591 roof[23]/cts[23]/tstb[23] u2 592 tdat[23] u3 593 tsync[23]/tstuff[23] u4 594 tclk[23] t1 597 rclk[23] t3 598 rsync[23]/rstuff[23] t4 599 rdat[23] r1 600 roof[22]/cts[22]/tstb[22] r2 603 tdat[22] r3 604 tsync[22]/tstuff[22] r4 607 tclk[22] p1 608 rclk[22] p2 609 rsync[22]/rstuff[22] p3 610 rdat[22] p4 611 roof[21]/cts[21]/tstb[21] n1 612 tdat[21] n2 613 tsync[21]/tstuff[21] n3 614 tclk[21] n4 615 rclk[21] m1 618 rsync[21]/rstuff[21] m3 619 rdat[21] m4 620 roof[20]/cts[20]/tstb[20] l1 623 tdat[20] l2 pad# name package ball 624 tsync[20]/tstuff[20] l3 625 tclk[20] l4 626 rclk[20] k1 627 rsync[20]/rstuff[20] k2 628 rdat[20] k3 629 roof[19]/cts[19]/tstb[19] k4 630 tdat[19] j1 631 tsync[19]/tstuff[19] j2 632 tclk[19] j3 635 rclk[19] j4 636 rsync[19]/rstuff[19] h1 637 rdat[19] h3 638 roof[18]/cts[18]/tstb[18] h4 639 tdat[18] g1 640 tsync[18]/tstuff[18] g2 643 tclk[18] g3 644 rclk[18] g4 647 rsync[18]/rstuff[18] f1 648 rdat[18] f2 note(s : 1. 166 ground (gnd)pads 2. 32 core supply pads (vddc)-1.8v 3. 32 output supply pads (vddo)-3.3v 4. 2 protection circuit esd (vgg) pad# name package ball table 9-3. signals (7 of 7)
cx28560 data sheet 28560-DSH-001-B mindspeed technologies? 9-12 advance information 101302_025 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al am an ap ar at au av aw a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al am an ap ar at au av aw 123456789101112131415161718192021222324252627282930313233343536373839 gnd gnd gnd gnd 9 13 19 23 29 33 38 42 48 52 58 64 67 72 78 82 86 90 95 101 105 111 116 122 125 131 137 142 148 154 157 gnd gnd gnd gnd gnd gnd gnd gnd 10 14 20 24 30 gnd 39 43 49 53 59 gnd 68 73 79 83 87 gnd 96 102 106 112 117 gnd 126 132 138 143 149 gnd 160 gnd gnd gnd gnd gnd gnd gnd gnd 11 15 21 27 31 36 40 46 50 54 60 65 69 74 80 84 88 93 99 103 107 113 118 123 129 133 139 144 150 155 161 gnd gnd gnd gnd gnd gnd gnd gnd 12 16 22 28 32 37 41 47 51 57 61 66 71 77 81 85 89 94 100 104 110 115 119 124 130 136 141 147 151 156 162 gnd gnd gnd gnd gnd 4 5 6 gnd vddc vddc gnd vddo gnd vddc gnd vddo gnd vddc gnd vddo gnd vddc gnd vddo gnd vddc gnd vddo gnd vddc gnd vddo gnd vddc gnd vddo gnd 168 165 164 163 gnd 494 gnd 493 490 gnd vddo vddo gnd vddc gnd vddo gnd vddc gnd vddo gnd vddc gnd vddo gnd vddc gnd vddo gnd vddc gnd vddo gnd vddc gnd vddo gnd vddc vddc gnd 322 319 318 317 gnd gnd gnd 489 gnd 482 477 gnd 461 455 vddo 441 436 gnd 424 420 416 410 404 399 395 387 383 378 374 368 362 359 354 346 342 337 333 326 gnd gnd gnd gnd gnd gnd gnd gnd gnd 486 gnd 474 470 gnd 450 446 gnd 435 431 422 419 413 409 403 398 394 386 382 377 373 367 361 357 351 345 339 336 332 325 323 gnd gnd gnd gnd gnd gnd gnd gnd 485 481 gnd 465 460 gnd 445 440 434 428 gnd 418 412 406 gnd 397 391 385 gnd 376 372 366 gnd 356 350 344 gnd 335 328 gnd 324 gnd gnd gnd gnd gnd gnd gnd gnd gnd 478 471 464 456 449 444 439 gnd 427 421 417 411 405 400 396 390 384 379 375 369 363 360 355 349 343 338 334 327 gnd gnd gnd gnd gnd gnd 647 648 gnd 3 vddo vddc 173 171 170 169 639 640 643 644 vddo vddc 181 178 177 176 636 gnd 637 638 gnd gnd 186 185 gnd 182 630 631 632 635 vddc vddo 190 189 188 187 626 627 628 629 gnd gnd 198 195 194 193 620 623 624 625 vddo vddc 202 201 200 199 615 gnd 618 619 gnd gnd 205 204 gnd 203 611 612 613 614 vddc vddo 211 210 207 206 607 608 609 610 gnd gnd 217 216 215 214 599 600 603 604 vddo vddc 223 222 221 218 594 gnd 597 598 gnd gnd 227 225 gnd 224 590 591 592 593 vddc vddo 233 232 229 228 586 587 588 589 gnd gnd 237 236 235 234 578 579 582 583 vddo vddc 243 240 239 238 573 gnd 574 575 gnd gnd 246 245 gnd 244 567 568 571 572 vddc vddo 250 249 248 247 561 564 565 566 gnd gnd 256 255 252 251 555 558 559 560 vddo vddc 260 259 258 257 550 gnd 551 554 gnd gnd 265 264 gnd 263 544 545 546 549 vddc vdd0 269 268 267 266 538 539 542 543 gnd gnd 273 272 271 270 532 533 536 537 vddo vddc 280 277 276 274 527 gnd 528 531 gnd gnd 285 282 gnd 281 521 522 525 526 vddc vddo 291 290 287 286 516 519 gnd 520 gnd gnd 297 296 295 294 511 gnd 512 515 vddo vddc 303 302 301 298 gnd 507 gnd 508 gnd gnd 306 305 gnd 304 506 503 502 gnd vddc vddo 312 309 308 307 499 gnd 498 496 vddc vddo 316 315 314 313 123456789101112131415161718192021222324252627282930313233343536373839 figure 9-1. pin diagram
28560-DSH-001-B mindspeed technologies? a - 1 advance information appendix a: counters the cx28560 provides the system with a complete set of management information base (mib) counters per channel in both the receive and transmit directions. each counter is 24 bits wide and satu rates on reaching its maximum value. a.1 one-second pin the one-second pin is an input to the cx28 560 that provides the boundaries of each latching period. the system can choose to send a pulse on this pin at any (not necessarily constant) interval. the maximu m value a counter can take is 24?hffffff. this is sufficient for a minimum of one second?s worth of data on any legally configured channel. this may suffice for longer ti me periods for low bit-rate channels. amount of time counters will suffice = (maximum value of counter) / (number of times the event occurs per second) example 1, the octet co unter for a t1 channel. amount of time counter will suffice = (24?hffffff)/44736000*8 = 3 seconds example 2, the octet counte r for a 52 mbps channel. amount of time counter will suffice = (24?hffffff)/6500000 = 2.58 seconds
a-2 mindspeed technologies? 28560-DSH-001-B advance information counters cx28560 data sheet a.2 counter latching counters are latched within a negligible delay of a puls e on the onesec pin. the latching of counters implies that the values are held in the background to be read by the system, and updates (during the next latching period) are made to an active set of counters. note that th e system does not need to keep track of which set of counters is the background because the cx28560 controls the intern al addressing; externally, both sets of counters are at the same ad dress. the values held in the background counters are overwritte n when the next one-second puls e is received. the latching of all counters is simultaneous, and the latched values can be read by a service routine request. on activation and deactivation of a channel, all counters related to that channel are set to zero.
28560-DSH-001-B mindspeed technologies? a - 3 advance information cx28560 data sheet counters a.3 counter descriptions a.3.1 receive counters in the receive direction, the followin g counters are provided per channel:  octet counter: ? a count of all octets received for this channel. this coun t does not include hdlc flags, abort sequences, or idle codes. the count does include fcs bytes and message data of all me ssages received including errored messages.  message counter: ? a count of all non-errored messages received for a channel. an errored message would either fall into one of the categories below, or have been discarded mid-message due to local conditions (i.e., due to a cofa or oof condition being detected or an intern al fifo overflow occurring). errored messages that are not discarded due to local conditions are counted in the counters below.  alignment error counter: ? a count of all messages that arrive containing an alignment error. an message containing an alignment error is defined as a message that, after removal of hdlc flags and hdlc zero insertions, contains a number of bits not divisible by eight.  fcs error counter: ? a count of all messages that arrive containing an fcs error.  abort condition counter: ? a count of all messages that arrive en ding in an abort condition. in this case, an abort condition is consider ed to be seven consecutive ones.  too long counter: ? a count of all messages that arrive that are longer than the maximum length. the maximum length of a r eceived message can be adjusted by selecting one of three 14-bit register s that define a limit for the maximum number of bytes allowed in the message.  too short counter: ? a count of all messages that are consid ered too short. a short message is a message with less th an the minimum of an 8-bit payload between two flags (e.g., at least 3 message bytes must be received in 16-bit fcs). too short also includes errors such as abort, cofa, oof, alignment and fcs in the case that no data had yet been transferred to the buffer controller from the rslp. a.3.1.1 multiple errors on a single message each message is only counted once according to the following priority: 1. abort condition 2. too long message 3. message alignment error 4. fcs error 5. no error occurs that is to say, a message containing both an fcs error and alignment error is counted only once in the alignment error counter.
a-4 mindspeed technologies? 28560-DSH-001-B advance information counters cx28560 data sheet a.3.2 transmit counters in the transmit direction, the follow ing counters are provided per channel:  octet counter: ? a count of all octets transmitted fo r this channel. this count does not include hdlc flags, abort sequences, or idle codes. the count does include fcs bytes and message da ta, including data of messages that were ultimately aborted.  message counter: ? a count of all messages transmitted for a channel.  aborted message counter: ? a count of all messages received from the system terminating in an abort command.
28560-DSH-001-B mindspeed technologies? a - 5 advance information cx28560 data sheet counters a.4 reading counters the reading of the values of latched counters is performed via service routine requests over the pci. a.4.1 receive direction in the receive direction, th e channels are arranged in the cx28560?s memory in groups of 8 register addresses (7 counters + 1 reserved). to re ad all counters for channel n, create a service request routine with the fields listed in table a-1 . table a-1. service request routine field for counter read (receive) descriptor field size description opcode 5 config_rd sackien 1 0?sack interrupt disabled. 1?sack interrupt enabled. an appropriate interrupt is genera ted after the comm and is completed. length 14 number of double words in the memory transaction request. if 0, the number of transfers is 16 k. therefore it allows for any number of dwords of 1?16384. to read all the receive counters for one channel, this should be set to 8. to read all the counters of all the channels, this should be set to 16384. shared memory pointer 30 + 2 shared memory ba se address for a memory transaction request. the pointer is dword-aligne d by concatenating two ze ros to the lsb and making it a 32-bit pointer. this address is set according to the system?s needs. cx28560 base 22 + 2 the cx28560 base (dword-aligned) address for a memory transaction request. the cx28560 base addresses are specified in bytes but dword-aligned, i.e., with the 2 lsbs as 00. to read channel n?s counters, this shoul d be set to (suffixed by 00 for dword alignment): (counter base address = 22?h008000) + (8 * n) to read all the channels? counters, this should be set to (s uffixed by 00 for dword alignment): (counter base address = 22?h008000)
a-6 mindspeed technologies? 28560-DSH-001-B advance information counters cx28560 data sheet the counters will be written to the shared memory as listed in table a-2 . a.4.2 transmit direction in the transmit direction, the channels are arranged in the cx28560 memory in groups of 4 register addresses (3 co unters + 1 reserved). in orde r to read all counters for channel n, a service request routine should be created with the fields listed in table a-3 . table a-2. receive counters in shared memory 31:24 23:0 reserved octet counter reserved message counter reserved alignment error counter reserved fcs error counter reserved abort condition counter reserved too long message counter reserved too short message counter reserved reserved table a-3. service request routine field for counter read (transmit) descriptor field size description opcode 5 config_rd sackien 1 0 = sack interrupt disabled. 1 = sack interrupt enabled. an appropriate interrupt is genera ted after the command is completed. length 14 number of double words in the memory transaction request. if 0 the number of transfers is 16k. the refore it allows for any number of dwords of 1?16384. to read all transmit counters for one channel, this should be set to 4. to read all the counters of all channels, this should be set to 8192. shared memory pointer 30 + 2 shared memory ba se address for a memory transaction request. the pointer is dword-aligned by conc atenating two zeros to the lsb and making it a 32-bit pointer. this address is set according to the system?s needs. cx28560 base 22 + 2 the cx28560 base (dword-ali gned) address for a memory transaction request. the cx28560 base addresses are specifie d in bytes but dword aligned i.e., with the 2 lsbs as 00. to read channel n?s counters, this should be set to (s uffixed by 00 for dword alignment): (counter base address=22?h008000) + (4 * n) to read all the channels? counters, this should be se t to (suffixed by 00 for dword alignment): (counter base address = 22?h008000)
28560-DSH-001-B mindspeed technologies? a - 7 advance information cx28560 data sheet counters the counters will be written to the shared memory as listed in table a-4 . table a-4. transmit counters in shared memory 31:24 23:0 reserved message counter reserved octet counter reserved abort command counter reserved reserved
a-8 mindspeed technologies? 28560-DSH-001-B advance information counters cx28560 data sheet
28560-DSH-001-B mindspeed technologies? b - 1 advance information appendix b: flexiframe algorithm b.1 overview the aim of the flexiframe algorithm is to facilitate the static allocation of internal memory between channels, such that each channel, regardless of its bit rate, will require an equal amount of memory (see appe ndix e: calculation of buffer size). in order to do this, channels of a higher bit rate are serviced, in proportion to their bit rate, more often than lower bit rate channels. a full implementation of the flexiframe algorithm is included in the cx28560 drivers (code can be provided on request). note: when all channels are of the same bit rate, the flexiframe algorithm takes its most simple form?a list of the channels. the following description ap plies to both the receive and transmit flexiframes. the flexiframe algorithm provides a sc hedule according to which the cx28560 services channels. the flexiframe is a list of the channels written to the cx28560 memory that, together with various user -configurable registers, fixes the buffer controller work mode. the flexiframe is a simple list of channel numbers in slots. each slot contains one channel number or nop command (slot channel number = 0), and represents one service by the buffer controller. in the receive direction, du ring each slot/service a maximum of one fragment of message data and fragment header will be sent over the pos-phy to the system. during a service the buffer of the channel whose number was the next in the flexiframe is examined. if the buffer contai ned either the end of a message or enough data to form a fragment, data ia sent to th e system. the length of the fragment sent is fixed in a receive buffer controller register (see chapter 5.0 ). in the transmit direction, during each slot/s ervice the transmit buffer controller sends a report to the system over the flow cond uctor pos-phy interface regarding the next channel in the flexiframe to be served (see appendix c, flow conductor). the parameters that can be fixed in the cx 28560 that control the flexiframe are as follows:  fragment length (receive only) the maximum number of 256 bytes per fragmen t. according to this value, the receive buffer controller decides whether enough data has been collected to send a fragment. enough data is defined to be either the number of 4-bytes as shown in the reference fragment length register (see section 5.7.8 rbuffc fragment size register ), or the existence of an end of message if one appear s before this amount of data is reached.  slot time (receive and transmit)
b-2 mindspeed technologies? 28560-DSH-001-B advance information flexiframe algorithm cx28560 data sheet the minimum number of system clock cy cles (at 100 mhz) that each buffer controller will spend on a given slot in the flexiframe. the number of clock cycles actually used will depend on the length of the fragment, the fact that 4 bytes are transmitted per clock, and that after each fra gment there is a break of 4 cycles before the next fragment is started. in the receive direction, if th e fragment length register has a larger value than the slot time or is less than 4 lower than the slot ti me, fragments will be transmitted with a gap of 4 cycles between them. if the fragment leng th register is lower than the slot time by more than 4, a fragment will be transmitted every slot time. in the transmit direction, the system tran smits fragments over the pos-phy data bus a maximum of once per slot time; if the fragme nt takes longer to transfer than the slot time, the slot time is extended. once per slot time, a channel number is read from the flexiframe, and an update report is sent to the system over the flow conductor pos- phy bus.  flexiframe length (receive and transmit) the maximum length of a flex iframe is 21,504 entries. the actual length of the flexiframe produced by the algorithm should be written to the relevant register (see chapter 5.0 ). b.2 new flexiframe required a new flexiframe is required when one of the following is necessary:  a new channel is to be activated  reset of the chip b.3 algorithm b.3.1 splitting channel bit rates into groups to provide a software efficient algorithm, channels are organized into groups/tables according to their bit rates and standard ra nge definitions. this allows any channel bit rate to be considered as one of a standard number (9) of bit rates. the standard range definitions are based on a binary system, whereby each range limit is half the bit rate of the previous limit. for example, the fastest channel is of bit rate 52 mbps, so the limits of the top group are 52 mbps and 26 mbps. any channel bit rate falling between these two limits will be treated as if it is a channel of bit rate 52 mbps. any channel falling into the next category (13 mbps?26 mbps) will be treated as a 26 mbps channel, etc. the standard limits are: #define limit0_152 #define limit1_226 #define limit2_313 #define limit3_46.5 #define limit4_53.25 #define limit5_61.625 #define limit6_70.813 #define limit7_80.406 #define limit8_90.203 #define limit9_100.101
28560-DSH-001-B mindspeed technologies? b - 3 advance information cx28560 data sheet flexiframe algorithm to calculate the number of clocks between services necessary for the group (as calculated for the highest bit rate for the group), the follow ing is considered. the slots allocated per channel will be sepa rated by a standard step size for each group. the standard step size is calculate d according to the channel?s bit rate and the minimum number of accumulated bytes of data that will require servicing (average). b.3.2 harmonic bit rates the main inefficiency in the above division of bit rates is that a channel just above one of the limits is considered as a channel w ith double its actual bit rate. this can be avoided if harmonics are introduced. the ha rmonic method treats the mid-bit rate between the limits as a new boundary. thos e channels that fall between the lower limit and the mid-range limit are assigned to the group below and the group below that (thus treating it as a channel of bit rate of the mid-range value). the channels within the groups are treated the same rega rdless of whether they were assigned to that group due to being in th e upper half of the group?s li mits, or due to being in the lower half of the group above.
b-4 mindspeed technologies? 28560-DSH-001-B advance information flexiframe algorithm cx28560 data sheet b.3.3 calculating st ep size per group assume that packet data is transferred in fragments of length fraglen, and that the receive direction the slot time register (see chapter 5.0 ) is set to fraglen + 4 words. the transfer of a p acket of size (fraglen + 1 words) will use the pos-phy and flexiframe bandwidth usua lly occupied by 2 complete fragments. hence in order to withstand the bandwidth wastage caused in the worst case scenario of packets of length fraglen + 1, a channel should be serviced at a frequency that allows the accumulation of 1/2 fraglen worth of data. if then this interval (stepsize) is calculat ed for the first group (that which treats each of its channels as if it were a 52 mbps channel), this wi ll provide the minimum step size. other step sizes are multiples of the minimum step size (due to binary allocation). for example, the fragment length is set in the register (see chapter 5.0 ) as 14, (each fragment is of length 32 bytes), and the slot time is set to be 20 system clock cycles (200 ns). the gap between each service of a 52 mbps channel is calculated according to the number of slots it will take the channe l to accumulate 28 b of data. this amount of time is 4307 ns, which is the equivalent of 430 clock cycles. each clock cycle is 200 ns, hence the number of slots between services for a 52 mbps channel is 21. due to the binary allocation, it is then simple mathematics that a channel in the next group down requires servicing every 42 slots (2 * 21), etc. table b-1. the flexiframe structure ... block m 1 2 3 4 .. n 1 2 3 4 .. n block 1 block 2 1 2 3 4 .. n 1 2 3 4 .. n min step size slot track 2 101302_013
28560-DSH-001-B mindspeed technologies? b - 5 advance information cx28560 data sheet flexiframe algorithm the flexiframe is split into blocks, each block containing minstepsize slots. each block is split into minstepsize tracks, where the first slot in each block is allocated to the first track, the second slot in each block to the second track, etc. b.3.4 assigning channels to slots/tracks in the assignment of the channels to the slots, these rules should be followed:  the channels should be assigned on a group-by-group basis, assigning the channels from the fastest group first an d then in decreasing bit-rate order;  each track should be filled completely befo re a new track is started. note that a channel in the first group will occupy an entire track (slots assigned at an interval of minstepsize), a channel in the second group will occupy half a track (slots assigned at an interval of 2 * minstepsize), etc. hence, a track can be fully occupied by 1 channel from group 1, 2 channels from group 2, 2 n-1 channels from group n; or any suitable combinatio n of the above (for example, 1 channel from group 2, 1 channel from group 3, and 2 channels from group 4). b.4 pseudo-code the input to the algorithm consists of two lists: chinput and bwinput, which must be of the same length. the output is the list of channel numbers: ch output. in an interim step, input channels are classifi ed into one of eleven groups. b.4.1 assigning input channels to groups for each (ch, bw) in (chinput, bwinput) do if (bw in [39 .. 52]) then add ch to group[0] else if (bw in [26 .. 39]) then add ch to group[1] add ch to group[2] else if (bw in [19.5 .. 26]) then add ch to group[1] else if (bw in [13 .. 19.5]) then add ch to group[2] add ch to group[3] else if (bw in [9.75 .. 13]) then add ch to group[2] else if (bw in [6.5 .. 9.75]) then add ch to group[3] add ch to group[4] else if (bw in [4.875 .. 6.5]) then add ch to group[3] else if (bw in [3.25 .. 4.875]) then
b-6 mindspeed technologies? 28560-DSH-001-B advance information flexiframe algorithm cx28560 data sheet add ch to group[4] add ch to group[5] else if (bw in [2.438 .. 3.25]) then add ch to group[4] else if (bw in [1.625 .. 2.438]) then add ch to group[5] add ch to group[6] else if (bw in [1.219 .. 1.625]) then add ch to group[5] else if (bw in [0.813 .. 1.219]) then add ch to group[6] add ch to group[7] else if (bw in [0.609 .. 0.813]) then add ch to group[6] else if (bw in [0.406 .. 0.609]) then add ch to group[7] add ch to group[8] else if (bw in [0.304 .. 0.406]) then add ch to group[7] else if (bw in [0.203 .. 0.304]) then add ch to group[8] add ch to group[9] else if (bw in [0.152 .. 0.203]) then add ch to group[8] else if (bw in [0.101 .. 0.152]) then add ch to group[9] add ch to group[10] else if (bw in [0 .. 0.101]) then add ch to group[9] end if end for
28560-DSH-001-B mindspeed technologies? b - 7 advance information cx28560 data sheet flexiframe algorithm b.4.1.1 computing the number of tracks to be used each track is 1024 slots long, and up to 21 tracks are interleaved in one flexiframe structure. this step computes the number of tracks needed, acco rding to the channel group sizes that were comput ed in the previous step. numtracks = 0.0 for i in [0 .. 10] do numtracks += group[i].size() / (2^i) end for numtracks = round to next integer (numtracks) if numtracks > 21 then return ?error: bad combination of channel bandwidths.? end if
b-8 mindspeed technologies? 28560-DSH-001-B advance information flexiframe algorithm cx28560 data sheet b.4.2 building the output allocate an output list of length (1024 * numtracks) fill the output list with empty slots (channel number 0) curtrack = 0 curtrackutilization = 0.0 curfirst = 0 for i in [0 .. 10] do curseparation = numtracks * (2^i) for each ch in group[i] do if curtrackutilization < 1.0 then // find an empty slot in the current track: while output[curfirst] <> empty do curfirst += numtracks end while else // get the first slot in the next track: curtrack++ curfirst = curtrack curtrackutilization = 0.0 end if // update track utilization curtrackutilization += 1 / (2^i) // insert the channel number in the output for j in [0 .. 2^(10-i)-1] do output [curfirst + curseparation*j] = ch end for end for end for
28560-DSH-001-B mindspeed technologies? b - 9 advance information cx28560 data sheet flexiframe algorithm b.5 analysis this analysis is based a number of fixed parameters. if these parameters are to be changed, the analysis should be performed with the new values. the fixed parameters are:  fragment length of 32 bytes (plus 4 header bytes)  slot time of 20 cycles to arrive at the minimum frame size requir ed for all configurations, the analysis was performed several times until a minimum was reached. this document only includes the proof that a 21,504 slot flexiframe will suffice, and not that this is the minimum required. table b-2 forms the basis for the analysis. containe d in it are the bit-rate group limits, variable allocation to group ranges, and th e number of slots to be allocated to each variable in a 21,504 slot flexiframe. table b-2. flexiframe analysis parameters channel max bandwidth [mbps] step size number of slots in a 21,504 frame variable (number of channels in the [range] [mbps]) 52 21 1024 a [52 ? 39] 39 (mid range) 42 + 84 512 + 256 b [39 ? 26] 26 42 512 c [26 ? 19.5] 19.5 (mid range) 84 + 168 256 + 128 d [19.5 ? 13] 13 84 256 e [13 ? 9.75] 9.75 (mid range) 168 + 336 128 + 64 f [9.75 ? 6.5] 6.5 168 128 g [6.5 ? 4.875] 4.875 (mid range) 336 + 672 64 + 32 h [4.875 ? 3.25] 3.25 336 64 i [3.25 ? 2.438] 2.438 (mid range) 672 + 1344 32 + 16 j [2.438 ? 1.625] 1.625 672 32 k [1.625 ? 1.219] 1.219 (mid range) 1344 + 2688 16 + 8 l [1.219 ? 0.813] 0.813 1344 16 m [0.813 ? 0.609] 0.609 (mid range) 2688 + 5376 8 + 4 n [0.609 ? 0.406] 0.406 2688 8 o [0.406 ? 0.304] 0.304 (mid range) 5376 + 10752 4 + 2 p [0.304 ? 0.203] 0.203 5376 4 q [0.203 ? 0.152] 0.152 (mid range) 10752 + 21504 2 + 1 r [0.152 ? 0.101] 0.101 10752 2 s [0.101 ? 0.064] 0.064 (min) ? ? ?
b-10 mindspeed technologies? 28560-DSH-001-B advance information flexiframe algorithm cx28560 data sheet b.5.1 equations for analysis to prove that a 21,504 flexiframe is a sufficient number of slots for any legal configuration of the cx28560, it is necessary to state the rules of a legal configuration and to express them mathematically: a. the number of channels is equal or less than 2047: a + b + c + d + e + f + g + h + i + j + k + l + m + n + o + p + q + r + s < 2048 b. the maximum bandwidth that can enter the cx28560 is 700 mbps: 39 * a + 26 * b + 19.5 * c + 13 * d + 9.75 * e + 6.5 * f + 4.875 * g + 3.25 * h + 2.438 * i + 1.625 * j + 1.219 * k + 0.813 * l + 0.609 * m + 0.406 * n + 0.304 * o + 0.203 * p + 0.152 * q + 0.101 * r + 0.064 * s <= 700 note that for each range the number of ch annels in the range is multiplied by the lower limit of the range because this limit is the worst case. the number of slots in the frame is eq ual or less then the frame size ? 21504: 1024 * a + 512 * (b + c) + 256 * (b + d + e) + 128 * (d + f + g) + 64 * (f + h + i) + 32 * (h + j + k) + 16 * (j + l + m) + 8 * (l + n + o) + 4 * (n + p + q) + 2 * (p + r + s) + 1 * r <= 21504 b.5.2 solution for equations equations (a) and (b) were entered into li near-programming prob lem solving software together with a command to find the maximum value of equation (c) under the constraints of (a) and (b). the maximum value of the last equation fo und was 20,899. hence, a 21,504 is large enough to encompass the required slot assignment for any configuration of channel bit rates that conforms to th e first 2 equations (less than 2028 channels, and aggregate bit rate less than or equal to 700 mbps).
28560-DSH-001-B mindspeed technologies? b - 11 advance information cx28560 data sheet flexiframe algorithm b.5.3 building the flexiframe the following equations show th at if the flexiframe is built according to the guidance outlined above, building a flexiframe for any legal configuration of the cx28560 is possible: it has been shown above that in 21,504 slots the following is true: 1. a = 1024 a + 768 b + 512 c + 384 d + 256 e + 192 f + 128 g + 96 h + 64 i + 48 j + 32 k + 24 l + 16 m + 12 n + 8 o + 6 p + 4 q + 3 r + 2 s <= 21,504 now considering the first 10,752 slots of the frame. if the frame is to be built, the following must be true: 2. b = 512 a + 384 b + 256 c + 192 d + 128 e + 96 f + 64 g + 48 h + 32 i + 24 j + 16 k + 12 l + 8 m + 6 n + 4 o + 3 p + 2 q + r + s <= 10752 since (1) has been proven, and all of the following are true: a = 2 b + r a <= 21,504 r >= 0 by simple substitution the following holds: 2 b + r <= 21,504 b <= 10,752 hence equation (2) holds. the same method of substitution and compar ison can be used to show that all the following equations are true: 3. 256 a + 192 b + 128 c + 96 d + 64 e + 48 f + 32 g + 24 h + 16 i + 12 j + 8 k + 6 l + 4 m + 3 n + 2 o + p + q <= 5,376 4. 128 a + 96 b + 64 c + 48 d + 32 e + 24 f + 16 g + 12 h + 8 i + 6 j + 4 k + 3 l + 2 m + n + o <= 2,688 5. 64 a + 48 b + 32 c + 24 d + 16 e + 12 f + 8 g + 6 h + 4 i + 3 j + 2 k + l + m <= 1344 6. 32 a + 24 b + 16 c + 12 d + 8 e + 6 f + 4 g + 3 h + 2 i + j + k <= 672 7. 16 a + 12 b + 8 c + 6 d + 4 e + 3 f + 2 g + h + i <= 336 8. 8 a + 6 b + 4 c + 3 d + 2 e + f + g <= 168 9. 4 a + 3 b + 2 c + d + e <= 84 10. 2 a + b + c <= 42 11. a <= 21 the above set of equations therefore show that if, when building a flexiframe, the rules outlined are followed, it will always be possible to build a flexiframe.
b-12 mindspeed technologies? 28560-DSH-001-B advance information flexiframe algorithm cx28560 data sheet
28560-DSH-001-B mindspeed technologies? c - 1 advance information appendix c: flow conductor interface c.1 overview the flow conductor interface provides the system with the information required to control the rate of the flow of data to the transmit buffer controller. this is necessary because the system has no other way to know the amount of data presently in the cx28560?s buffers?the line bit rate of the channel does not provide this information because hdlc processing can cause a significant skew from the line rate. information is provided to the system in th e form of reports of the number of words sent or removed from the buffer since the last report was sent together with the relevant channel number. thus, the system can maintain a set of counters, one per channel, of the amount of space available in each channel?s internal buffer. the counters are initialized to the size of the buff er on channel activation, then each report received from the cx28560 increments the counters, and each fragment sent by the system to the cx28560 causes the relevant co unter to be decremented. the only other consideration is the storage of a message?s last fragment header (that contains the message command bits). this header is st ored in 2 bytes in the channel?s buffer according to figure c-1 .
c-2 mindspeed technologies? 28560-DSH-001-B advance information flow conductor interface cx28560 data sheet if the length of the payload in a fragment is fraglen, the number of 4 bytes a fragment occupies can be calculated as follows: if the fragment is not the last fragment in a packet, it will occupy (fraglen / 4) 4 bytes in the internal buffer. if the fragment is the la st fragment in a packet, the number of 4 bytes it will occupy is as follows: in case fraglen % 4 = 1, num_4bytes = (fraglen + 3) / 4; in case fraglen % 4 = 2, num_4bytes = (fraglen + 2) / 4; in case fraglen % 4 = 3, num_4bytes = (fraglen + 5) / 4; in case fraglen % 4 = 4, num_4bytes = (fraglen + 4) / 4; figure c-1. data and command storage in internal buffer 0 31 command 0 31 data data data data 0 31 command 0 31 data data data 0 31 data data command 0 31 data command fragment length % 4 = 1 fragment length % 4 = 2 fragment length % 4 = 3 fragment length % 4 = 4
28560-DSH-001-B mindspeed technologies? c - 3 advance information cx28560 data sheet flow conductor interface c.2 example take, for example, a channel that has just b een activated, so the internal buffer is empty. the free space counter for that channe l should be set to the size of the buffer allocated in the buffer size register ( chapter 5.0 , rbuffc data fifo size register). fraglen is the number of bytes in the fragment. when a fragment of length fraglen is sent to the cx28560, not containing an end of message, the free space coun ter should be decremented by fraglen / 4 (this will be the whole number maxfraglen/4). when a fragment of length fraglen is sent to the cx28560, containing an end of message, the free space counter should be decremented by: switch (fraglen % 4) case 1: (fraglen + 3) / 4 case 2: (fraglen + 2) / 4 case 3: (fraglen + 5) / 4 case 4: (fraglen + 4) / 4 when a report is received, the counter should be incremented by the value received in the report of the number of words sent (wsent). this value of wsent takes into consideration the storage of command bytes in the internal buffer, so no further calculation is required.
c-4 mindspeed technologies? 28560-DSH-001-B advance information flow conductor interface cx28560 data sheet
28560-DSH-001-B mindspeed technologies? d - 1 advance information appendix d: tsbus d.1 connection between cx28560 and other tsbus device this section details the si gnals required to implem ent the tsbus interface. figure d-1 illustrates the tsbus connectio ns between the other device and cx28560. the signals requ ired are summarized in tables d-1 and d-2 . the tsbus consists of the payload and the overhead bus. each bus has a transmit and receive path. the receive path is defined from the other device to cx28560, and the transmit path is defined from cx28560 to the other device. cx28560 can only generate the tsb_tsync i signal during non-stuffed transmit payload time slots. cx28560 must not ge nerate the tsb_tsynci signal during stuffed transmit payload time sl ots. a stuffed transmit payload time slot is defined as the eighth tsbus payload byte following the assertion of a payload transmit stuff signal.
d-2 mindspeed technologies? 28560-DSH-001-B advance information tsbus cx28560 data sheet figure d-1. cx28560 time slot interface pins cx29503 cx28560 p a y l o a d o v e r h e a d p a y l o a d o v e r h e a d tsb_clk tsb_tstuff tsb_tdat tsb_rstuff tsb_rdat tsb_stb tsb_clk tsb_tstuff tsb_tdat tsb_rstuff tsb_rdat tsb_stb tsb_tsynco tsb_tsynci tclk tstuff tdat rclk rstuff rdat tstb tclk tstuff tdat rclk rstuff rdat tstb tgsync 51.84/44.736 mhz 12.96/11.184 mhz 100579_021 tsb_rsync rgsync
28560-DSH-001-B mindspeed technologies? d - 3 advance information cx28560 data sheet tsbus table d-1. system side interface: payload time slot bus symbol reset behavior i/o definition tsb_clk low out payload time slot bus clock: this cl ock is based on sib_txhscl k. it is used for all timing on the payload time slot bus. clock rate is 51.84 mbps ( 20 ppm) tsb_stb low out payload time slot bus strobe: a strobe signal that indicates the start of a frame with 84 time slots carrying payload data. the st robe indicates the beginning of each payload time slot frame. tsb_tdat ? in payload time slot bus transmit data: thi s is the serial payload da ta to be received by tsbus. this signal is sampled on the rising edge of tsb_clk. tsb_tstuff high out payload time slot bus transmit stuff indication: wh en high, indicate s a stuff byte must be transmitted in place of the data byte arriving 8 time slots later. tsb_rdat low out payload time slot bus receive data: this is the received serial payload data. it is transmitted from tbus on the rising edge of tsb_clk. tsb_rstuff high out payload time slot bus receive st uff indication: when high, indicates that data on tsb_rdat is not valid data. tsb_rdat is stuffed with all 1s. table d-2. system side interface: overhead time slot bus symbol reset behavior i/o definition tsb_oclk low out payload time slot bus clock: this cl ock is based on sib_txhscl k. it is used for all timing on the payload time slot bus. clock rate is 51.84 mbps ( 20 ppm) tsb_ostb low out payload time slot bu s strobe: a strobe signa l that indicates the start of a frame with 84 time slots carrying payload data. the st robe indicates the beginning of each payload time slot frame. tsb_otdat ? in payload time slot bus transmit data: thi s is the serial payload da ta to be received by tsbus. this signal is sampled on the rising edge of tsb_clk. tsb_otstuff high out payload time slot bus transmit stuff indication: wh en high, indicate s a stuff byte must be transmitted in place of the data byte arriving 8 time slots later. tsb_ordat low out payload time slot bus receive data : this is the received ser ial payload data. it is transmitted from tsbus on the rising edge of tsb_clk. tsb_orstuff high out payload time slot bus receive st uff indication: when high, indicates that data on tsb_rdat is not valid data. tsb_rdat is stuffed with all 1s.
d-4 mindspeed technologies? 28560-DSH-001-B advance information tsbus cx28560 data sheet figure d-2. source/destination of tsbus block line-side signals electrical e3 electrical ds3 sonet sts-1 spe sonet sts-1 spe sonet sts-1 spe sonet sts-1 spe sdh au-3 sdh au-3 tsbus tsbus tsbus tsbus tsbus/ e1 framer tsbus/ e1 framer tsbus (c-11)/ ds1 framer tsbus (c-12)/ e1 framer e3 e2 e1 14 416 17 428 17 4 74 28 28 7321 7321 7428 17 321 ds3 ds2 ds1 ds3 ds2 ds1 ds3 ds2 ds1 vtg vt1.5 vtg vt2.0 tug-2 tu-11 tug-2 tu-12 28560_031
28560-DSH-001-B mindspeed technologies? d - 5 advance information cx28560 data sheet tsbus d.1.1 vsp mapping of intermix ed digital level 2 signals the following digital level 2 signals can tr ansport either ds1 or e1 signals: vtg, tug-2, and ds2. sonet, sdh, and pdh tr ansport their respective level 2 signals in sets of seven level 2 signals. this set of seven level 2 signals can operate in mixed mode where a portion of the seven level 2 multiplexed signals transport ds1 signals and the remainder transport e1 signals. an y given level 2 signal in mixed mode can only transport ds1 signals or e1 signals. it cannot transport both signals. table d-4 defines the mapping of ds1 and e1 signals when they are extracted from a mixed set of seven vtgs, a mixed set of se ven tug-2s, or a mixe d set of seven ds2s. each level 2 signal has a set of 3 or 4 relate d framers. all framers within a set must be configured for the same type of signal. this prevents framers for different data paths from multiplexing data into the same time slot. there are four framers in a set for ds1, vt1.5, and vc-11 signals. there are three framers in a set for e1, vt2.0, and vc-12 signals. the types of level 2 signals that can be mi xed together are limit ed to the following combinations: 1. ds2 signals containing ds1 signals and the ds2 signals containing e1 signals. 2. vtg signals containing vt1.5, which contain ds1 signals and vtg signals containing vt2.0, which contain e1 signals. 3. tug-2 signals containing vc-11, wh ich contain ds1 signals and vtg-2 signals containing vc-12, which contain e1 signals. table d-3. system side interface: overhead time slot bus frame tsbus source/destination overhead data communication channel mapped to virtual serial port (vsp) description data rate ds1/e1 framer no. 1-28 f-bit data link/sa4 bit data link 112 kbps sts-12/sts-3/stm-1 mapper regenerator section data communication channel (dccr) bytes 1?3 194 kbps sts-12/sts-3/stm-1 mapper mul tiplex section (line) data communication channel (dccm) bytes 1?9 583 kbps sonet/sdh sds-1/au-3 mapper pat h user channel: f2 64 kbps sonet/sdh sts-1/au-3 mapper path user channel: f3 64 kbps sonet/sdh sts-1/au-3 mapper spe/au path ov erhead nibble n1 (4 lsbs) path data channel/bit oriented or lapd tandem connection 32 kbps unused communication time slots future use 3.564 mbps command status processor (csp) tb us register management 6.48 mbps
d-6 mindspeed technologies? 28560-DSH-001-B advance information tsbus cx28560 data sheet table d-4. vsp mapping of intermixed digital level 2 signals containing either ds1 or e1 signals framer set no. framer no. concatenated time slot numbers vsp no. framer configured to extract ds1 signal framer configured to extract e1 signal 1 1 1, 29, 57 1, 22, 43 64 1 2 2 2, 30, 58 2, 23, 44, 65 2 3 3 3, 31, 59 3, 24, 45, 66 3 4 4 4, 32, 60 4, 25, 46, 67 4 5 5 5, 33, 61 5, 26, 47, 68 5 6 6 6, 34, 62 6, 27, 48, 69 6 7 7 7, 35, 63 7, 28, 49, 70 7 1 8 8, 36, 64 8, 29, 50, 71 8 2 9 9, 37, 65 9, 30, 51, 72 9 3 10 10, 38, 66 10, 31, 52, 73 10 4 11 11, 39, 67 11, 32, 53, 74 11 5 12 12, 40, 68 12, 33, 54, 75 12 6 13 13, 41, 69 13, 34, 55, 76 13 7 14 14, 42, 70 14, 35, 56, 77 14 1 15 15, 43, 71 15, 37, 57, 78 15 2 16 16, 44, 72 16, 37, 58, 79 16 3 17 17, 45, 73 17, 38, 59, 80 17 4 18 18, 46, 74 18, 39, 60, 81 18 5 19 19, 47, 75 19, 40, 61, 82 19 6 20 20, 48, 76 20, 41, 62, 83 20 7 21 21, 49, 77 21, 42, 63, 84 21 1 22 22, 50, 78 na 22 2 23 23, 51, 79 na 23 3 24 24, 52, 80 na 24 4 25 25, 53, 81 na 25 5 26 26, 54, 82 na 26 6 27 27, 55, 83 na 27 7 28 28, 56, 84 na 28 note(s): framers with the same set number must be configured for the same data signal (i.e., all framers within a set must be configured for ds1 or e1 signals but not both).
28560-DSH-001-B mindspeed technologies? d - 7 advance information cx28560 data sheet tsbus d.2 timing details d.2.1 payload bus, ac characteristics the tsbus device operates as the mast er of the transmit tsbus and the cx28560 (hdlc controller) device re sponds as slave. tsbus generates tsbus clocks and control signals an d the cx28560 device responds by transmitting tsbus data to or receiving tsbus data from tsbus. tsbus generates a tsbus frame strobe (tsb_stb) on the rising edge of tsb_clk as seen in figure d-2 . the time slot bus frame strobe tsb_stb indicates the start of an n time sl ot frame carrying payload data. the time slot bus exchanges data over two i/o chip boundaries so care must be taken in ensuring that the data is exch anged on the right phase of the master tsbus clock tsb_clk. a possible solution for ensuring correct data exchange is for the slave (cx28560) to transmit data on the rising edge of tsb_clk, and sample the received data on the falling edge of tsb_clk. there is only one time slot frame st robe used (tsb_stb) for transmit and receive direction. there is also only one clock (tsb_clk) used in the definition of bit boundaries for transmit and receive. this results in the time slot frame alignment of the receive and transmit payload (illustrated in figure d-2 ). each time slot in the time slot bus consists of eight serial data bits. the msb bit for each time slot is transmitted first.
d-8 mindspeed technologies? 28560-DSH-001-B advance information tsbus cx28560 data sheet d.2.2 transmit timing the tsbus device operates as the mast er of the transmit tsbus, and the cx28560 device responds as slave. th e tsbus generates clock, frame sync signal, and stuff signal. cx 28560 will generate transm it data (tsb_tdat) or generate an all-1s stuff pattern eight time slots after receiving an active stuff signal. the tsbus will generate a fr ame sync strobe (tsb_stb) output synchronously with the rising edge of tsb_clk. figure d-3 illustrates the timing requirements for the transmit. figure d-3 illustrates the stuff signal. the target timing values are listed in table d-4 . figure d-3. payload time slot bus transmit data (tsb_tdat) 2 8560_033 tsb_clk tsb_tdat transmit bit n transmit bit n+1 transmit bit n+2 t per t pwh t pwl t s t h
28560-DSH-001-B mindspeed technologies? d - 9 advance information cx28560 data sheet tsbus figure d-4. payload time slot bus transmit stuff indicator (tsb_tstuff) tsb_clk tsb_tstuff tsb_tdat bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 msb lsb 8500_034 time slot #n (8 bits of serial data) byte 1 byte 2 byte 3 byte 4 byte 5 byte 7 byte 6 byte 8 stuffed time slot the byte arriving 8 time slots (bytes) after tsb_stuff is expected to be stuffed
d-10 mindspeed technologies? 28560-DSH-001-B advance information tsbus cx28560 data sheet d.2.3 receive timing the tsbus device operates as the ma ster of the receive tsbus and the cx28560 device responds as slave. th e tsbus generates clock, data, frame sync signal, and the stuff signal. the tsbu s generates an all ones stuff pattern in place of the payload data during the same ti me slot that the stuff signal is active. the tsbus generates control and data ou tputs synchronously with the rising edge of tsb_clk. the nominal clock frequency is 51.84 mbps. figure d-5 shows the timing requirements for the receive interface. see figure d-6 for the stuff signal. figure d-5. payload time slot bus receive data (tsb_rdat) 8500_035 tsb_clk tsb_rdat receive bit n receive bit n+1 receive bit n+2 t per t pwh t pwl
28560-DSH-001-B mindspeed technologies? d - 11 advance information cx28560 data sheet tsbus figures d-7 through d-9 provide timing diagrams for tsb_tsynco, tsb_tsynci, and tsb_rsync. these diagrams show that tsb_tsynci, tsb_tsynco, and tsb_rsync are currently defined as bit-wide signals when asserted. the cx28560 only uses tsb_tsynci and tsb_rsync, not tsb_tsynco. figure d-6. payload time slot bus receive stuff indicator (tsb_rstuff) 8500_035 tsb_clk tsb_rdat receive bit n receive bit n+1 receive bit n+2 t per t pwh t pwl
d-12 mindspeed technologies? 28560-DSH-001-B advance information tsbus cx28560 data sheet figure d-7. tsbus interface to cx28560 transmit sync timing (tsb_tsynco) tsb_stb tsb_tdat ts #2 .... ts #30 .... ts #3 ts #56 ts #22 .... .. tsb_clk ts #1 ts #1 ts #2 frame #1 ds0_1 frame #1 ds0_3 frame #1 ds0_4 frame #3 ds0_1 frame #2 ds0_1 frame #2 ds0_2 frame #2 ds0_3 first ds0 byte of ds1 frame #1 first ds0 byte of ds1 frame #3 first ds0 byte of ds1 frame #2 13 24 7 6 58 ... .... 2 1 .... tsb_tsynco tsb_tdat time slot #1 ( 8 bits of serial data) with first ds0 byte of ds1 frame #1 tsb_stb .... ts #58 ts #57 ts #84 ts #83 ts #82 ts #81 ts #84 ts #79 ts #78 ts #77 ts #80 tsb_tsynco .... .... .... .... .... ... .... 8 bytes (64 bits) late 8500_047
28560-DSH-001-B mindspeed technologies? d - 13 advance information cx28560 data sheet tsbus figure d-8. tsbus interface to cx28560 transmit sync timing (tsb_tsynci) tsb_stb tsb_tdat tsb_tsynci ts #2 .... ts #30 ts #29 ts #3 .... ts #58 ts #57 ts #56 ts #28 ...... tsb_clk ts #1 ts #1 ts #84 ts #2 frame #1 ds0_1 frame #1 ds0_2 frame #1 ds0_3 frame #1 ds0_4 frame #3 ds0_1 frame #2 ds0_1 frame #2 ds0_2 frame #2 ds0_3 first ds0 byte of ds1 frame #1 first ds0 byte of ds1 frame #3 first ds0 byte of ds1 frame #2 13 24 7 6 58 ... .... 2 1 .... tsb_tsynci tsb_tdat time slot #1 ( 8 bits of serial data) with first ds0 byte of ds1 frame #1 tsb_stb 8500_048
d-14 mindspeed technologies? 28560-DSH-001-B advance information tsbus cx28560 data sheet figure d-9. tsbus interface to cx28560 receive sync timing (tsb_rsync) tsb_rdat ts #2 .... ts #30 ts #29 ts #3 .... ts #58 ts #57 ts #56 ts #28 ...... ts #1 ts #1 ts #84 ts #2 frame #1 ds0_1 frame #1 ds0_2 frame #1 ds0_3 frame #1 ds0_4 frame #3 ds0_1 frame #2 ds0_1 frame #2 ds0_2 frame #2 ds0_3 first ds0 byte of ds1 frame #1 first ds0 byte of ds1 frame #3 first ds0 byte of ds1 frame #2 13 24 7 6 58 ... .... 2 1 .... tsb_rdat time slot #1 ( 8 bits of serial data) with first ds0 byte of ds1 frame #1 tsb_stb tsb_rsync tsb_clk tsb_rsync tsb_stb 8500_049
28560-DSH-001-B mindspeed technologies? d - 15 advance information cx28560 data sheet tsbus d.3 overhead bus, ac characteristics same operation as the payload tsbus, only difference is the tsb_oclk rate of 12.96 mbps compared to the payload rate of 51.84 mbps. d.3.1 transmit timing see section d.2.2 . d.3.2 receive timing see section d.2.3 .
d-16 mindspeed technologies? 28560-DSH-001-B advance information tsbus cx28560 data sheet
28560-DSH-001-B mindspeed technologies? e - 1 advance information appendix e: buffer controller fifo size calculation e.1 introduction this appendix aims to prov e that there exists a maximum buffer size required to contain the information in the buffer cont roller, and to calculate that maximum. the analysis is based on the flexifra me algorithm and the cx28560 receive buffer controller design. fuller explan ations can be found in the relevant documentation. the proof applies to 56 -byte fragments, and a minimum packet length of 40 bytes. extrapol ation to other values for these parameters is provided via example at the end of the analysis. e.1.1 terminology flexiframe is the algorithm used to implement a channel service scheduler. rslp?receive serial line processor. block that interfaces with the buffer controller providing a maximum of 32 bits of data and one 8-bit message status per system clock. an overflow is said to have occurred when new data/status arrives from the rslp and there is no further sp ace available in the fifo.
e-2 mindspeed technologies? 28560-DSH-001-B advance information buffer controller fifo size calculation cx28560 data sheet figure e-1 illustrates the fifo. overhead bytes contain space reserved for the fragment head er, and the space reserved for last by tes when appropriate. y t is the number of overhead bytes in fragment t. data bytes contain the message data received from the rslp. x t is the number of data bytes in fragment t. n is the number of fragments in the fifo ready for transmissi on to the system. e.1.2 assumptions the minimum message size is 40 bytes. messages that are shorter than this may cause the buffer to overflow under some conditio ns (continuous reception of short messages at line rate is sufficient). this assump tion also applies to a stream of aborted messages. figure e-1. buffc internal fifo 101302_015 overhead overhead overhead data data data fragment 0 (initial bytes) fragment 1 fragment n ...
28560-DSH-001-B mindspeed technologies? e - 3 advance information cx28560 data sheet buffer controller fifo size calculation e.1.3 overkill the analysis presented in the continuation of this document does not take into account any hdlc processing of data when calcul ating amounts of data received by the cx28560. the hdlc processing includes the following:  zero insertions?a maximum of an extra 1/6 of the data received by the rslp is not passed to the buffer controller?though a minimum of 0? hence not overkill;  at least one flag is received per message?negligible affect in long messages, but for the short messages used in the analysis they have a larger affect? overkill; therefore, for every message co nsidered to have arrived, 1 input byte will be removed (the equivalent of removing one flag per message).  crc bytes?0, 2, or 4 bytes that may or may not be passed to the buffer controller. since they may be passed to the buffer controller they are not overkill. however, due to the architect ure, the rslp passes to the buffc one of the data/status combinations listed in table , . the passing of the status later than the data can only be caused by the rslp removing crc bytes and detecting a flag. because this would require the removal of 2 bytes from the possible data that could arrive, this situation is not includ ed in the analysis. table e-1. data/status combinations state data_hi data_low 0 x status x x x 1xstatusx xdata 2 x status x data data 3 x status data data data 4 x data data data data 5 status data data data data
e-4 mindspeed technologies? 28560-DSH-001-B advance information buffer controller fifo size calculation cx28560 data sheet e.2 expanding data in because the worst case scenario involves mi d-range channels (to maximize amount of data between services), examples of data expansion have only been provided for mid- range channels. e.2.1 ending a 57-byte message this accumulation requires 32 bytes in th e fifo. note the next message header and last bytes are not accumulated because 1 by te that entered the fifo was a flag from the end of the 57-byte message. hence, 41 data bytes entered (1 byte to finish 57-byte message plus 40 message bytes). this is not enough for the closing flag of the 40+ byte message. (buffc thinks it is still in the middle of storing the message). 101302_017 56 b mesg 40 b mesg 42 b accumulated between services 1 b header bytes (4 b) space for last bytes (4 b) key
28560-DSH-001-B mindspeed technologies? e - 5 advance information cx28560 data sheet buffer controller fifo size calculation e.2.2 byte message this accumulation requires 32 bytes in the fi fo: 8 bytes for header and last bytes, 40 bytes for message that arrive d (plus one flag byte). this time, the place for header and last bytes is set aside because there ar e enough bytes for the closing flag of the 40-byte message to have arrived. e.2.3 ending a fragment wi th no end of message this accumulation requires 52 bytes in the fifo. e.2.4 not ending a fragment this accumulation requires 44 bytes in the fifo. hence, maximum number of fifo bytes th at a 42-byte in can require is 56 bytes. 101302_018 40 b mesg 40 b mesg 42 b accumulated between services 1 b 101302_019 56 b fragment 41 b fragment 42 b accumulated between services 101302_020 <56 b fragment 42 b accumulated between services
e-6 mindspeed technologies? 28560-DSH-001-B advance information buffer controller fifo size calculation cx28560 data sheet e.3 general buffer wastage most wasteful in terms of bytes => 57-byte messages most wasteful in terms of tr ansactions => 57-byte messages conclusion: if a buffer that has been fi lled with 57-byte messages can successfully converge to a solution, any other co mbination will similarly converge. e.4 overview of analysis e.4.1 preliminary calculations  calculate maximum amounts of data that can arrive between services.  calculate maximum number of services that can be missed due to algorithms used. mesg len bytes in fifo % waste 45 52 13.5 41 48 14.6 56 60 6.7 57 68 16.2 61 72 15.3 mesg len bytes in fifo # trans trans/mesg byte trans/fifo byte 45 52 1 0.022 0.019 41 48 1 0.024 0.021 56 60 1 0.018 0.017 57 68 2 0.035 0.029 61 72 2 0.033 0.028
28560-DSH-001-B mindspeed technologies? e - 7 advance information cx28560 data sheet buffer controller fifo size calculation e.5 receive analysis  calculate buffer size required to contain all data that will arrive due to missed services.  compare amounts of data received between services and amount removed by service to check that it is not necessary to enlarge the buffer to take extra data received into account.  show that the sequence of servicing converges for 57-byte messages a check whether, at any point, the sequence requires a larger buffer than the minimum.  if, at the end of 6 services, the amount of data in the fifo and the amount of space used in the fifo is less than the initial conditions, proof has worked. e.5.1 preliminaries e.5.1.1 missed services the analysis assumes that the worst possible st arting position is that a channel that has been allocated mid-range steps has just misse d a service when it accumulates its next fragment for transmission. the scenario con tinues that the missed service was the last time that the channel was to be serviced in the frame, and the system has written a new frame to the memory. figure e-2 illustrates this specific worst case on a frame. figure e-2. worst case on a frame 101302_021 old frame service 2*service 2*service (a) service 2*service 2*service service service new frame service(b)
e-8 mindspeed technologies? 28560-DSH-001-B advance information buffer controller fifo size calculation cx28560 data sheet between points (a) and (b), up to 84 byte s of data may accumulate (42 bytes between each service). the 42 bytes comes from the following: due to the mid-range, in the worst case, each channel that uses the mid range receives (x + x / 2) = 3x / 2 services in a frame according to its bw, (while x is the number of services for the lower cl osest full range). th e number of bytes received per frame is 28 b * 3x / 2 = 42 b * x. x services are guaranteed to receive service with constant slots between them; thus, the worst distance between two services is 42 bytes. at (a) the channel fifo contains initial bytes amount of data. the extra bytes accumulated for the frame swap ping only needs to be included in the calculation once. this is because the next time the frame is swapped, the maximum amount of time between the last time a se rvice could have taken place and the first service of the frame is one step size. henc e, the amount of data accumulated in the buffer is reduced, and the next time the frame is swapped, the extra accumulated data will be stored in the freed bytes from the previous over-allocation. figure e-3 illustrates servicing a mid-range channel. note the above is an absolute worst case b ecause the first time the channel is serviced, it is serviced once and then must wait 42 bytes to be serviced twice in succession. figure e-4 illustrates servicing a normal channel. figure e-3. servicing a normal channel 101302_022 42 b 42 b 42 b 42 b 42 b 42 b 42 b 42 b 42 b figure e-4. worst case servicing of a mid-range channel 101302_023 28 b 28 b 28 b 28 b 28 b 28 b 28 b 28 b 28 b
28560-DSH-001-B mindspeed technologies? e - 9 advance information cx28560 data sheet buffer controller fifo size calculation e.5.2 calculation of step size between services the slots per channel are given with gaps, according to the chan nel bw. the gap size represents the time at which the channel a ccumulates 28 bytes of data in its specific bw. the 28 bytes that may accumulate is th e amount of data that, after expansion, will use the 32 bytes of data in a burst. th e expansion is due to the fact that a message length is not optimal to the 56-byte bursts. it may take 2 bursts to send a 56-byte message. the 2 bursts bw is 112 bytes, so the ratio between the original message size to the actual bw allocated for it is 112 / 56 = 2. example: th e accumulation of 28 bytes at a 52 mbps channel takes 4307 ns (4 31 clock cycles). a fast channel must be serviced every such period. it means that a fast channel is to be serviced every 431 / 20 = 21.55 slots -> 21 slots . e.5.2.1 starting position initial bytes + extra bytes due to missed service + extra bytes due to swapped frame initial bytes form one (or less fragment). extra bytes are 42 bytes each?a total of 84 extra bytes number of fragments available to be transf erred (not including initial fragment) = n each fragment contains x bytes of data and y bytes of overhead (headers, last bytes) where: 0 x 56 4 y 8 x 1 + ? + x n 84 x + y 60 x + y = initial bytes 60 in general, x 40. this is only not true when a full fragment is followed by a shorter end of message fragment. in this case: x 1 + x 2 56 there are 84 bytes entering the bloc k. these can be divided as follows: x 2 + all singular xs x 2 + 3 * x 3 n = 4 x 2 + all doubles x 2 + (x 1 + x 2 ) + x 1 n = 4 x 2 + single/double mix x 2 + x 3 + x 1 n = 3 (note in worst case x 2 = 0 at start of ?other?) hence, max n = 4. sum (x 1 : x 4 ) 84 sum (y 1 : y 4 ) 4 * max y = 32 hence, initially buffer contains: initial bytes + sum (x 1 : x 4 ) + sum (y 1 : y 4 ) 60 + 84 + 32 = 176 bytes minstepsize systemclock timeperslot --------------- ------------------ - fragmentsize 2 ------------------- ----------------- - 8 bitrate ----------------- - =
e-10 mindspeed technologies? 28560-DSH-001-B advance information buffer controller fifo size calculation cx28560 data sheet e.5.2.2 servicing a series of 56-byte messages may cause the am ount of data in the channel?s fifo to reach a steady state of full. this is acceptable because nothing can be done to tip the steady state in the direction of overfl ow, and eventually th e stream of 56-byte messages will either change to different size messages, or the channel will be deactivated. so now assuming that either the messages are shorter (w orst case 40-byte messages, or that they are longer?now worst case is 57-byte). figure e-5 illustrates worst case servicing of a mid-range channel (services maximum distance apart). servicing of a mid-range channel can be seen as repetitions of th e shaded grey area above; i.e., every 3 services plus 3 fillings the cycle is repeated. hence, if after 3 services and 3 fillings there is less data than at first, it could be on the way to a convergent solution (not least since bandwidth out > bandwidth in). e.5.2.3 57-byte messages reach end of first white area ?after that is repetitions. start position (takes into account flags): since start with both less data and le ss fifo bytes, can assume convergence. though minimum buffer required is 180 bytes to take into account state (f). e.5.2.4 last bit (byte) since during the service of a channel (20 cycles), a fast ch annel can accumulate a byte which in turn could take an extra row in the fifo, an extra 4 bytes of space must be added to the maximum calculated above. this gives a buffer space of 184 bytes per channel, or total of 368 kb. figure e-5. worst case servicing of a mid-range channel 101302_024 56, 1, 56, 1, 24 168, 140 a 32 bytes out 1, 56, 1, 24 108, 82 b 42 bytes in 1, 56, 1, 56, 1, 8 160, 123 c1, 32 bytes out 1, 56, 1, 8 92, 66 d 42 bytes in 1, 56, 1, 50 136, 108 e1 byte out 56, 1, 50 128, 107 f 42 bytes in 56, 1, 56, 1, 35 180, 149 g 56, 1 bytes out 56, 1, 35 112, 92 h 42 bytes in 56, 1, 56, 1, 20 164, 134
28560-DSH-001-B mindspeed technologies? e - 11 advance information cx28560 data sheet buffer controller fifo size calculation e.5.3 example because the minimum buffer size required per channel is dependent on a number of independent parameters (minimum packet size, existence of mid-range channels, likeness of channels configured), the next paragraph provides an example for the calculation of the minimum buffer size. it is recommended that the characteristics of the system be decided and the buffer si ze be calculated according to these characteristics. e.5.3.1 channels of same bit rate, large minimum packet size in this example, the bit-rate of the channel and mid-range considerations are irrelevant, because the flexiframe will be a simple list of th e channels. hence the above calculation is overkill. for fragme nts of length fraglen bytes, the time between two consecutive services is guaranteed to be less than the time a channel will take to accumulate 1/2 fraglen bytes of data. assuming that the minimum packet length (minpktlen) is less than the fragment length, and th at initially there is one fragment and 2 missed services, the sequence of servicing in table e-2 will lead to the equation for the number of channels configurable for a specified fraglen. since we start with both less data and less fifo bytes, we can assume convergence. assuming that the minimum fr agment size is 32 bytes, the minimum buffer size required is created in stage (a), i.e., that of 2 * fraglen + 12. note: an additional 4 bytes should be added if, during the configured slot time, a channel can accumulate an extra byte of data. from this equation and the fact that th ere is 384 kb of memory available for allocation between channels, the maximum nu mber of channels configurable for a specific fragment size can be calculated: number of channels configurable = (384 * 1024) / (2 * fraglen + 12 + 4) note: if the minimum packet size is known to be smaller than the fragment size, this may affect the size of buffer required for each channel and this should be taken into account. table e-2. servicing sequence stage action buffer content (services) buffer content (bytes) (a) start position fraglen, 1, fr aglen ? 1 2 * fraglen + 3 * 4 (b) fraglen out 1, frag len -1 fraglen + 2 * 4 (c) ? fraglen in 1, fr aglen, 1, (1/2 fraglen ?1) (3 / 2)fraglen + 4 * 4 (d) 1 out fraglen, 1, (1/2 fraglen ?2) (3 / 2)fraglen ? 1 + 4 *4 (e) ? fraglen in fraglen, 1, (frag len ?2) 2 * fraglen ? 1 + 3 * 4
e-12 mindspeed technologies? 28560-DSH-001-B advance information buffer controller fifo size calculation cx28560 data sheet e.6 transmit fifo calculation e.6.1 service request scheme reports are sent to the system containing a count of the number of double words that were delivered to the tslp since the last request (including cmnd dwords). the cx28560 sends reports for a channel accordin g to the flexiframe algorithm, as long as the channel is activated and overflow did not occur. the system should maintain an empty dword counter for each channel, wh ich will indicate how many empty dwords the cx28560?s buffer has for that channel. for each request from the cx28560, the system first updates the empty byte count for this channel and decides if it can deliver another fragment of data or not, according to the next amount of data it has to deliver (see appendix c: flowconductor). if a threshold (configurable per channel) has been passed or if a full message is in the buffer, the cx28560 starts transmitting packets. in case of all packets of 40 bytes or 57 bytes, at the beginning of the transmissi on the channel does not transmit at full speed until the buffer has been filled. th is occurs each time the buffer becomes empty, and starts transmitting packets of 40 bytes or 57 bytes at full speed. the slow down in a channels transmission rate may also occur when the frame is changed at worst case conditions. in normal operation there also may be a temporary slowdown in the channel?s rate when the packet size changes from short to long (due to the time until threshold dwords are filled to start transmitting the new packet). the transition from long pack ets to 57-byte packets (without taking into consideration the frame change effect) will cause no slowdown of the channel bit rate. a slowdown in a channel?s rate can also oc cur when the packets are shorter than 28 bytes (this is the minimum size of fragments that can hold a full rate under the flexiframe scheme for this buffer size). buffer calculations:  for a 52-mbps channel: 60 b (base) + 28 b (missed request) + 28 b (frame change) + 5 s (latency)* 52 mbps/8= 60 b (base) + 28 b (missed request) + 28 b (frame change) + 33 b (latency) = 149 b -> 152 b (to be divided by 4) (181 b with 10 s latency)  for a 39-mbps channel: (mid range): 60 b (base) + 42 b (missed request) + 42 b (frame change) + 5 s (latency)*39 mbps / 8 = 6 b (base) + 42 b (missed request) + 42 b (frame change) + 25 b (latency) = 169 b->172 b (to be divided by 4) (193 b with 10 s latency)
28560-DSH-001-B mindspeed technologies? e - 13 advance information cx28560 data sheet buffer controller fifo size calculation explanation:  other wastes: ? indication bits: cmnd (command bit) -> 43(dwords per channel) * 2047 / 8 ~11 kb added. if we use the same buffer size for all chan nels, for 2 k-1 channels we will need: 5 s latency: 172-byte (data buffer size) * 2047 + 11 kb(cmnd bit) = 354.84 kb (per channel = 43 dwords of data +43 cmnd bits)) note: notes: all slower channels will have the same value for frame change and will consume fewer buffers only due to a smaller latency affect. base the minimum size of buffer needed beyond the trn threshold. it is needed because the system does not send a fragment of data even if it has only 1 byte to send unless there is enough place for a full fragment size (32 bytes for normal fragment + 4-byte cmnd). missed request if a request is missed beca use there was not enough space for a full fragment, until the next request opportunity the txslp will transmit more data at the mean time. frame change when the frame is changed, a service opportunity of a certain channel can be moved, so th e channel might miss a request opportunity to a frame change. the request opportunity may be maximum moved in one service opportunity distance, so the affect is the same as missed request. latency the latency affect from the fragment request time until it is received. the latency specified here is the maximum time that passes from the request opportunity (slot time) until the whole fragment is received, stored at the data fifo and all the write memory information is updated internally. the actual time that passes since the request is put out on the prx_out until the fragment is received on the ptx_ in should be less then that
e-14 mindspeed technologies? 28560-DSH-001-B advance information buffer controller fifo size calculation cx28560 data sheet
28560-DSH-001-B mindspeed technologies? f - 1 advance information appendix f: example of little-big endian byte ordering an example of little-big-endian byte orderi ng is shown in the next table. for the example a 32-bit dword was used?76543210h: note: when little-big-endian byte ordering is used, this only refers to the data portion of the interface to the host, meaning that only data transfers are affected. table f-1. little endian address x+3 x+2 x+1 x data 76h 54h 32h 10h table f-2. big endian address x+3 x+2 x+1 x data 10h 32h 54h 76h
f-2 mindspeed technologies? 28560-DSH-001-B advance information example of little-big endian byte ordering cx28560 data sheet
28560-DSH-001-B mindspeed technologies? g - 1 advance information appendix g: example of an arbitration for fast and non-fast back-to-back transactions figure g-1 illustrates, in a specific configura tion, cx28560?s pci transactions while operating as a master, and fa st back-to-back feature enabled. cx28560 performs as a master while operating at 32-bit address- data, a burst write of 2 dwords, which are transferred during the first cycle and a burst write of 3 dwords, which are transferred during the second cycle. both transaction cycles require 4 pclk cycles. figure g-1. pci burst write: two 32-bit fast back-to-back transactions to same target clk frame# ad[31:0] c/be#[3:0] par irdy# trdy# devsel# address data1 address data1 data3 data2 data2 bus cmd be1 bus cmd be1 be3 be2 be2
g-2 mindspeed technologies? 28560-DSH-001-B advance information example of an arbitration for fast and non-fast back-to-back transactions cx28560 data sheet figure g-2 illustrates how cx28560 operates at 32-bit address-data and performs a burst read of 2 dwords transfer during the first cycle and 3 dwords transfer during the second cycle. the fast back-t o-back feature is disabled. it can be observed that the first cycle takes 5 pclk cycles (with one pclk post-data phase) and the second cycle of transfer ring 3 dwords requires 6 pclk cycles. figure g-2. pci burst: two 32-bit transactions clk frame# ad[31:0] c/be#[3:0] par irdy# trdy# devsel# address data1 address data1 data3 data2 data2 bus cmd bus cmd be1 be1 be3 be2 be2
28560-DSH-001-B mindspeed technologies? h - 1 advance information appendix h: pci utilization h.1 overview this appendix will prov ide the system with an approxim ation of the util ization of one cx28560 on the 32 bit, 33 mhz pci bus. the calculations can be extrapolated, or tailored to the actual needs of the system. h.2 analysis it is assumed that the interrupts being wr itten by the cx28560 to the shared memory has a negligible affect on the pci utilization. in addition, the configuration of internal registers is also considered a negligible factor on the overall pci utilization. the major contributors to the cx28560 pci activi ty are the writing of flexiframes to the cx28560 (at 21 k entries each) and the reading of all the channels? counters once per second. h.2.1 internal considerations the time to perform a write or read of 32 bits is the total of:  internal wastage: ? this includes time for processing commands, internal bus time, and reaction time by the blocks. this is not a maximum figure, because no absolute maximum exists, only a statistical maximum. ? 70 clocks @ 100 mhz = 700 ns  pci bus time: ? the calculation below allows each entry in the flexiframe to be written, and each counter to be read in separate desc riptors. in addition, it allows for >20 cycle latency. ? 30 clocks @ 33 mhz = 900 ns hence the total time taken to perform one host service routine is 1600 ns (per 32-bit register).
h-2 mindspeed technologies? 28560-DSH-001-B advance information pci utilization cx28560 data sheet h.2.2 conditions assuming that, in the worst case, in one second the system will:  read 10 counters for 2047 channels (takes the time of reading 12) => 12 * 2047 * 1600  change the flexiframe 4 times (2 times transmit, 2 times receive) => 4 * 21 * 1024 * 1600 the total time to perform these command s is 0.176 seconds. hence the total utilization of one cx28560 is 0.176.
28560-DSH-001-B mindspeed technologies? i - 1 advance information appendix i: maximum number of channels calculation the maximum number of channels configurable is dependant on a number of parameters. in the analysis included in this specification, it is proven that for fragments of 56 bytes and a slot time of 20 cycles, for any dynamic combination of 2047 channels, a flexiframe can be built, and that sufficient buffering can be supplied. the simplest form of the calculation of the maximum numb er of channels configurable from the fragme nt length is by simple extrapolation from the above example, as follows:  a maximum of 2047 channels can be configured with a 56-byte fragment  a maximum of 1024 channels can be configured with a 112-byte fragment  a maximum of 512 channels can be configured with a 224-byte fragment this analysis (and therefor e the example above) provides for maximum flexibility in the allocation of channels bandwidths allowi ng the user to conf igure a channel with any bit rate. however by introducing the channels? bandwidt hs into the equation used to calculate the maximum number of channels, the length of the fragment can sometimes be increased. it can be seen in appendix e that the buffer calculation assumes half-rate allocations. for a known set of frequencies in the system a more efficient flexiframe structure can be created. this structure ca uses less oversubscribing and a service will be provided when needed. it will not use the half-rate method, as a result the buffer size needed for each channel w ill be smaller. it will be 68 + 64 + 24 = 156 bytes. in this case, the cx28560 can support 2 k ch annels with 64-byte fragments. longer fragments will force the max numb er of channels to be lower.
i-2 mindspeed technologies? 28560-DSH-001-B advance information maximum number of ch annels calculation cx28560 data sheet

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